<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Nanowire FET: wrap the gate all the way around the channel</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Gate-all-around gives the best electrostatics &#8212; stack the wires back to get the drive current</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; More gated sides</text><text x="32" y="106" fill="#8b949e" font-size="10.5">how much of the channel the gate touches</text><!-- planar --><rect x="42" y="150" width="44" height="16" rx="1" fill="#38506a"/><rect x="42" y="140" width="44" height="10" rx="1" fill="#d08a4a"/><text x="64" y="182" fill="#adb5bd" font-size="8.5" text-anchor="middle">planar</text><text x="64" y="194" fill="#8b949e" font-size="8" text-anchor="middle">1 side</text><!-- finfet --><rect x="128" y="134" width="30" height="40" rx="2" fill="#d08a4a"/><rect x="136" y="140" width="14" height="34" rx="1" fill="#38506a"/><text x="143" y="182" fill="#adb5bd" font-size="8.5" text-anchor="middle">FinFET</text><text x="143" y="194" fill="#8b949e" font-size="8" text-anchor="middle">3 sides</text><!-- gaa --><circle cx="204" cy="154" r="18" fill="#d08a4a"/><circle cx="204" cy="154" r="9" fill="#34d399"/><text x="204" y="182" fill="#7ee6c0" font-size="8.5" text-anchor="middle">GAA wire</text><text x="204" y="194" fill="#8b949e" font-size="8" text-anchor="middle">all around</text><!-- arrow of progression --><line x1="42" y1="210" x2="222" y2="210" stroke="#3f9d6f" stroke-width="1.2" marker-end="url(#nw)"/><text x="132" y="224" fill="#34d399" font-size="8.5" text-anchor="middle">tighter electrostatic control</text><text x="32" y="248" fill="#adb5bd" font-size="9.5">Wrapping the gate on every side lets</text><text x="32" y="263" fill="#adb5bd" font-size="9.5">it shut the channel completely: a</text><text x="32" y="278" fill="#adb5bd" font-size="9.5">steeper subthreshold slope and far</text><text x="32" y="293" fill="#adb5bd" font-size="9.5">less drain-induced leakage than a fin.</text><text x="32" y="316" fill="#8b949e" font-size="9.5">Copper = gate &#183; green = silicon channel.</text><text x="32" y="338" fill="#8b949e" font-size="9.5">This is the device behind the &#8220;GAA&#8221;</text><text x="32" y="353" fill="#8b949e" font-size="9.5">nanosheet node at 2nm-class logic.</text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; One wire is too thin</text><text x="279" y="106" fill="#8b949e" font-size="10.5">stack channels to add drive width</text><!-- single wire --><text x="322" y="130" fill="#adb5bd" font-size="9" text-anchor="middle">single wire</text><circle cx="322" cy="170" r="20" fill="#d08a4a"/><circle cx="322" cy="170" r="10" fill="#34d399"/><text x="322" y="204" fill="#8b949e" font-size="8" text-anchor="middle">low current</text><!-- stacked --><text x="426" y="130" fill="#7ee6c0" font-size="9" text-anchor="middle">stacked sheets</text><rect x="404" y="140" width="44" height="72" rx="8" fill="#d08a4a"/><rect x="412" y="150" width="28" height="10" rx="4" fill="#34d399"/><rect x="412" y="171" width="28" height="10" rx="4" fill="#34d399"/><rect x="412" y="192" width="28" height="10" rx="4" fill="#34d399"/><text x="426" y="224" fill="#7ee6c0" font-size="8" text-anchor="middle">3&#215; the width</text><line x1="352" y1="170" x2="398" y2="170" stroke="#8b949e" stroke-width="1" marker-end="url(#nw2)"/><text x="279" y="250" fill="#adb5bd" font-size="9.5">A lone nanowire has a tiny perimeter,</text><text x="279" y="265" fill="#adb5bd" font-size="9.5">so it carries little current. Stacking</text><text x="279" y="280" fill="#adb5bd" font-size="9.5">several sheets under one shared gate</text><text x="279" y="295" fill="#adb5bd" font-size="9.5">multiplies effective width in the same</text><text x="279" y="310" fill="#adb5bd" font-size="9.5">footprint &#8212; this is the nanosheet FET.</text><text x="279" y="333" fill="#8b949e" font-size="9.5">Sheet width is tunable: wide for drive,</text><text x="279" y="348" fill="#8b949e" font-size="9.5">narrow for low-power cells.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; How it&#8217;s built</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the Si / SiGe superlattice trick</text><circle cx="532" cy="126" r="2.4" fill="#9fd8ef"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Grow a superlattice</text><text x="542" y="143" fill="#8b949e" font-size="9">alternating Si and SiGe epitaxial</text><text x="542" y="156" fill="#8b949e" font-size="9">layers &#8212; Si becomes the channels.</text><circle cx="532" cy="176" r="2.4" fill="#34d399"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Release the channels</text><text x="542" y="193" fill="#8b949e" font-size="9">a selective etch removes the SiGe,</text><text x="542" y="206" fill="#8b949e" font-size="9">leaving suspended Si wires/sheets.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Wrap gate + inner spacer</text><text x="542" y="243" fill="#8b949e" font-size="9">high-k/metal fills all around each</text><text x="542" y="256" fill="#8b949e" font-size="9">sheet; spacers isolate it from S/D.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#e0b13a" font-size="10" font-weight="700">Nanowire &#8594; nanosheet &#8594; CFET</text><text x="536" y="306" fill="#adb5bd" font-size="9">The wire was the lab prototype; wide</text><text x="536" y="320" fill="#adb5bd" font-size="9">sheets made it manufacturable (GAA).</text><text x="536" y="334" fill="#adb5bd" font-size="9">Next, CFET stacks nMOS over pMOS</text><text x="536" y="348" fill="#adb5bd" font-size="9">sheets to fold the cell in half.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Gate-all-around</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Gate surrounds the channel on every</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">side &#8212; the tightest control possible.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Drive by stacking</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">More sheets = more width = more</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">current, with no extra floor area.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#e0b13a" font-size="11" font-weight="700">The GAA lineage</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Nanowire &#8594; nanosheet is how logic</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">moved past FinFET at 3/2nm.</text><defs><marker id="nw" markerWidth="7" markerHeight="7" refX="6" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#3f9d6f"/></marker><marker id="nw2" markerWidth="7" markerHeight="7" refX="6" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#8b949e"/></marker></defs></svg>

Nanowire FET Overview

Nanowire FET is a Gate-All-Around (GAA) transistor with cylindrical (wire-shaped) silicon channels fully surrounded by the gate electrode. It offers the best electrostatic control of any transistor geometry.

Nanowire vs. Nanosheet

• Nanowire: Circular/small cross-section (~5-10nm diameter). Best gate control but limited drive current per wire.
• Nanosheet: Wider rectangular cross-section (10-50nm wide). More drive current per sheet. Preferred by industry for production.
• Both are GAA: Gate wraps all four sides. Nanosheets are essentially wide nanowires.

Fabrication

1. Grow alternating Si/SiGe superlattice stack. 2. Pattern into narrow fin structures (< 10nm width creates wire-like cross-section). 3. Dummy gate patterning, spacer formation, S/D epitaxy. 4. Selective SiGe removal releases suspended Si nanowires. 5. Gate-all-around high-k/metal gate deposited wrapping each wire.

Advantages

• Superior electrostatic control: Near-ideal subthreshold slope (~62 mV/dec at room temp).
• Excellent short-channel effect suppression: DIBL < 30 mV/V.
• Low leakage: Gate fully controls the channel with no ungated surfaces.

Challenges

• Drive Current: Small cross-section limits current per wire. Must stack many wires (4-8) to get adequate drive.
• Variability: Small dimensional variations in wire diameter have large impact on threshold voltage.
• Parasitic Capacitance: Gate wrapping multiple wires in close proximity increases capacitance.