<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Nanowire FET: wrap the gate all the way around the channel</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Gate-all-around gives the best electrostatics &#8212; stack the wires back to get the drive current</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; More gated sides</text><text x="32" y="106" fill="#8b949e" font-size="10.5">how much of the channel the gate touches</text><!-- planar --><rect x="42" y="150" width="44" height="16" rx="1" fill="#38506a"/><rect x="42" y="140" width="44" height="10" rx="1" fill="#d08a4a"/><text x="64" y="182" fill="#adb5bd" font-size="8.5" text-anchor="middle">planar</text><text x="64" y="194" fill="#8b949e" font-size="8" text-anchor="middle">1 side</text><!-- finfet --><rect x="128" y="134" width="30" height="40" rx="2" fill="#d08a4a"/><rect x="136" y="140" width="14" height="34" rx="1" fill="#38506a"/><text x="143" y="182" fill="#adb5bd" font-size="8.5" text-anchor="middle">FinFET</text><text x="143" y="194" fill="#8b949e" font-size="8" text-anchor="middle">3 sides</text><!-- gaa --><circle cx="204" cy="154" r="18" fill="#d08a4a"/><circle cx="204" cy="154" r="9" fill="#34d399"/><text x="204" y="182" fill="#7ee6c0" font-size="8.5" text-anchor="middle">GAA wire</text><text x="204" y="194" fill="#8b949e" font-size="8" text-anchor="middle">all around</text><!-- arrow of progression --><line x1="42" y1="210" x2="222" y2="210" stroke="#3f9d6f" stroke-width="1.2" marker-end="url(#nw)"/><text x="132" y="224" fill="#34d399" font-size="8.5" text-anchor="middle">tighter electrostatic control</text><text x="32" y="248" fill="#adb5bd" font-size="9.5">Wrapping the gate on every side lets</text><text x="32" y="263" fill="#adb5bd" font-size="9.5">it shut the channel completely: a</text><text x="32" y="278" fill="#adb5bd" font-size="9.5">steeper subthreshold slope and far</text><text x="32" y="293" fill="#adb5bd" font-size="9.5">less drain-induced leakage than a fin.</text><text x="32" y="316" fill="#8b949e" font-size="9.5">Copper = gate &#183; green = silicon channel.</text><text x="32" y="338" fill="#8b949e" font-size="9.5">This is the device behind the &#8220;GAA&#8221;</text><text x="32" y="353" fill="#8b949e" font-size="9.5">nanosheet node at 2nm-class logic.</text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; One wire is too thin</text><text x="279" y="106" fill="#8b949e" font-size="10.5">stack channels to add drive width</text><!-- single wire --><text x="322" y="130" fill="#adb5bd" font-size="9" text-anchor="middle">single wire</text><circle cx="322" cy="170" r="20" fill="#d08a4a"/><circle cx="322" cy="170" r="10" fill="#34d399"/><text x="322" y="204" fill="#8b949e" font-size="8" text-anchor="middle">low current</text><!-- stacked --><text x="426" y="130" fill="#7ee6c0" font-size="9" text-anchor="middle">stacked sheets</text><rect x="404" y="140" width="44" height="72" rx="8" fill="#d08a4a"/><rect x="412" y="150" width="28" height="10" rx="4" fill="#34d399"/><rect x="412" y="171" width="28" height="10" rx="4" fill="#34d399"/><rect x="412" y="192" width="28" height="10" rx="4" fill="#34d399"/><text x="426" y="224" fill="#7ee6c0" font-size="8" text-anchor="middle">3&#215; the width</text><line x1="352" y1="170" x2="398" y2="170" stroke="#8b949e" stroke-width="1" marker-end="url(#nw2)"/><text x="279" y="250" fill="#adb5bd" font-size="9.5">A lone nanowire has a tiny perimeter,</text><text x="279" y="265" fill="#adb5bd" font-size="9.5">so it carries little current. Stacking</text><text x="279" y="280" fill="#adb5bd" font-size="9.5">several sheets under one shared gate</text><text x="279" y="295" fill="#adb5bd" font-size="9.5">multiplies effective width in the same</text><text x="279" y="310" fill="#adb5bd" font-size="9.5">footprint &#8212; this is the nanosheet FET.</text><text x="279" y="333" fill="#8b949e" font-size="9.5">Sheet width is tunable: wide for drive,</text><text x="279" y="348" fill="#8b949e" font-size="9.5">narrow for low-power cells.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; How it&#8217;s built</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the Si / SiGe superlattice trick</text><circle cx="532" cy="126" r="2.4" fill="#9fd8ef"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Grow a superlattice</text><text x="542" y="143" fill="#8b949e" font-size="9">alternating Si and SiGe epitaxial</text><text x="542" y="156" fill="#8b949e" font-size="9">layers &#8212; Si becomes the channels.</text><circle cx="532" cy="176" r="2.4" fill="#34d399"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Release the channels</text><text x="542" y="193" fill="#8b949e" font-size="9">a selective etch removes the SiGe,</text><text x="542" y="206" fill="#8b949e" font-size="9">leaving suspended Si wires/sheets.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Wrap gate + inner spacer</text><text x="542" y="243" fill="#8b949e" font-size="9">high-k/metal fills all around each</text><text x="542" y="256" fill="#8b949e" font-size="9">sheet; spacers isolate it from S/D.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#e0b13a" font-size="10" font-weight="700">Nanowire &#8594; nanosheet &#8594; CFET</text><text x="536" y="306" fill="#adb5bd" font-size="9">The wire was the lab prototype; wide</text><text x="536" y="320" fill="#adb5bd" font-size="9">sheets made it manufacturable (GAA).</text><text x="536" y="334" fill="#adb5bd" font-size="9">Next, CFET stacks nMOS over pMOS</text><text x="536" y="348" fill="#adb5bd" font-size="9">sheets to fold the cell in half.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Gate-all-around</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Gate surrounds the channel on every</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">side &#8212; the tightest control possible.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Drive by stacking</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">More sheets = more width = more</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">current, with no extra floor area.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#e0b13a" font-size="11" font-weight="700">The GAA lineage</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Nanowire &#8594; nanosheet is how logic</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">moved past FinFET at 3/2nm.</text><defs><marker id="nw" markerWidth="7" markerHeight="7" refX="6" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#3f9d6f"/></marker><marker id="nw2" markerWidth="7" markerHeight="7" refX="6" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#8b949e"/></marker></defs></svg>

Nanowire Transistor Process is the fabrication methodology for creating cylindrical or near-cylindrical silicon channels with diameters of 3-10nm and gate-all-around geometry — providing the ultimate electrostatic control for sub-5nm technology nodes by maximizing the gate-to-channel coupling through the highest surface-to-volume ratio of any transistor architecture, enabling operation at gate lengths below 8nm with near-ideal subthreshold characteristics.

Nanowire Formation Methods:

• Top-Down Patterning: start with Si fin structure; iterative oxidation-etch cycles thin the fin to nanowire dimensions; thermal oxidation at 800-900°C consumes Si (0.44nm Si → 1nm SiO₂); HF strip removes oxide; repeat 5-10 cycles to achieve 5-8nm diameter; diameter uniformity <1nm (3σ) challenging due to LER amplification
• Bottom-Up Growth: vapor-liquid-solid (VLS) mechanism using Au catalyst nanoparticles; SiH₄ precursor at 450-600°C; nanowire grows vertically from substrate; diameter controlled by catalyst particle size (5-50nm); single-crystal Si with <110> or <111> orientation; not compatible with CMOS fab due to Au contamination
• Superlattice Thinning: epitaxial Si/SiGe stack similar to nanosheet process; after SiGe release, thermal oxidation thins Si sheets to nanowire dimensions; oxidation consumes Si from all exposed surfaces; final diameter 4-8nm; circular cross-section achieved with optimized oxidation time/temperature
• Selective Epitaxial Growth: pattern catalyst sites or seed regions; selective Si epitaxy grows nanowires only from designated locations; diameter 10-30nm; vertical or horizontal orientation depending on growth conditions; integration with planar CMOS challenging

Horizontal Nanowire Integration:

• Channel Dimensions: nanowire diameter 5-8nm (3nm node), 3-5nm (2nm node); length equals gate length (10-15nm); multiple nanowires (3-6) stacked vertically with 12-15nm spacing; total effective width = π × diameter × number of wires
• Electrostatic Advantage: gate wraps completely around cylindrical channel; natural length scale λ = √(ε_si × t_ox × d_wire / 4ε_ox) where d_wire is diameter; for 6nm wire with 0.8nm EOT, λ ≈ 2nm enabling excellent short-channel control at 10nm gate length
• Quantum Confinement: 5nm diameter approaches 1D quantum wire regime; subband splitting 50-100 meV affects transport; effective mass modification changes mobility; ballistic transport fraction increases (mean free path ~10nm comparable to gate length)
• Fabrication Challenges: suspended nanowire mechanical stability; sagging under gravity for long spans (>100nm); surface roughness scattering dominates mobility (roughness <0.5nm RMS required); diameter variation directly impacts Vt (±1nm diameter → ±50mV Vt shift)

Vertical Nanowire Architecture:

• Bottom-Up Approach: nanowires grown vertically from substrate; gate wraps around vertical channel; S/D contacts at top and bottom; footprint = nanowire diameter (5-10nm) vs horizontal GAA footprint ~100-200nm²; 10-20× density advantage
• Top-Down Vertical Etch: deep Si etch (100-200nm) creates vertical pillars; diameter defined by lithography and etch trim; aspect ratio 10:1 to 20:1; etch profile control critical (sidewall angle >89°); diameter uniformity <10% required
• Gate Stack Wrapping: conformal ALD deposits HfO₂ and metal gate around vertical nanowire; step coverage >95% from bottom to top; gate length = vertical height of gate electrode (20-50nm); longer gate improves electrostatics but increases capacitance
• S/D Formation: bottom S/D formed in substrate before nanowire growth; top S/D formed by selective epitaxy or ion implantation after gate formation; contact resistance critical (vertical current path); silicide or metal contact at top

Process Integration Challenges:

• Inner Spacer for Nanowires: even more critical than nanosheet due to smaller dimensions; spacer thickness 2-3nm; conformal deposition on cylindrical surface; selective etch to remove from channel region while preserving between nanowire and S/D; SiOCN or SiCO deposited by ALD at 300-400°C
• Gate Stack Conformality: HfO₂ ALD must achieve >98% conformality (top:bottom thickness ratio) around 5nm diameter wire; precursor diffusion into narrow gaps between stacked wires; purge time 5-10× longer than planar process; deposition temperature <300°C to prevent nanowire oxidation
• Doping Challenges: ion implantation ineffective for 5nm diameter (straggle comparable to wire size); in-situ doped S/D epitaxy required; dopant activation anneal without nanowire oxidation or dopant diffusion; millisecond laser anneal or flash anneal at 1100-1200°C for <1ms
• Parasitic Resistance: nanowire resistance = ρ × L / (π × r²) scales unfavorably with diameter; 5nm diameter, 15nm length, ρ=1mΩ·cm → 190Ω per wire; requires 4-6 parallel wires to achieve acceptable resistance; S/D contact resistance dominates total resistance

Performance Characteristics:

• Drive Current: 3-wire stack with 6nm diameter achieves 1.2-1.5 mA/μm (normalized to footprint width) for NMOS at Vdd=0.75V; lower than nanosheet due to quantum confinement mobility degradation and higher series resistance
• Subthreshold Slope: 62-65 mV/decade maintained to 8nm gate length; DIBL <15 mV/V; off-state leakage <10 pA/μm; near-ideal electrostatics due to optimal gate coupling
• Variability: diameter variation is dominant source; ±0.5nm diameter variation → ±30mV Vt variation; line-edge roughness amplified during thinning process; statistical Vt variation σVt = 20-30mV for 6nm diameter wires
• Scaling Roadmap: 2nm node targets 4-5nm diameter with 4-5 wire stack; 1nm node may use 3nm diameter approaching quantum dot regime; vertical nanowire architecture becomes necessary for continued density scaling beyond 2nm

Nanowire transistor processes represent the ultimate evolution of silicon CMOS scaling — pushing electrostatic control to its physical limit through cylindrical gate-all-around geometry, but facing fundamental challenges from quantum confinement, surface roughness, and series resistance that may define the end of classical CMOS scaling in the early 2030s.