NBTI and HCI Transistor Reliability are the two dominant transistor aging mechanisms that cause threshold voltage shift and performance degradation over device lifetime — NBTI (Negative Bias Temperature Instability) degrades PMOS transistors under negative gate bias at elevated temperature by creating interface traps and oxide charges, while HCI (Hot Carrier Injection) degrades both NMOS and PMOS at high drain fields by injecting energetic carriers into the gate dielectric, both causing Vth drift that accumulates over billions of switching cycles in the 10-year lifetime target of consumer and automotive ICs.

NBTI (Negative Bias Temperature Instability)

• Occurs in: PMOS (VGS < 0, high |VGS|) at elevated temperature (70–125°C).
• Mechanism: Negative gate field + temperature → hydrogen from Si-H bonds at Si/SiO₂ interface → releases H → dangling bond (interface trap P_b center).
• Also: Oxide charge generation near interface → trapped holes → positive oxide charge.
• Effect: Both interface traps and oxide charges → increase |Vth| in PMOS → slower switching.
• Degradation: ΔVth ∝ t^n where n ≈ 0.15–0.25 (power law) and exponential in temperature.

NBTI Measurement

• Classic method: DC stress → measure Id-Vg → calculate ΔVth.
• Problem: NBTI partially recovers when stress removed → measurement delay underestimates damage.
• Fast measurement (OTF method): Measure Id during stress without removing bias → no recovery artifact.
• Lifetime extrapolation: Stress at high voltage → extrapolate ΔVth at 10-year, VDD nominal.

HCI (Hot Carrier Injection)

• Occurs in: NMOS (primarily) and PMOS at high VDS → high lateral electric field in channel.
• Hot carriers: Electrons (NMOS) or holes (PMOS) accelerated by drain field → gain energy → "hot".
• Impact ionization: Hot carrier collides with lattice → generates electron-hole pair.
• Injection: Hottest carriers gain enough energy to surmount SiO₂ energy barrier (3.1 eV for electrons) → inject into gate dielectric.
• Effect: Interface trap generation near drain → ΔVth, Δgm (transconductance degradation).
• HCI maximum: Occurs at VGS ≈ VDS/2 (maximum substrate current condition).

Comparison NBTI vs HCI

Reliability Models

• NBTI reaction-diffusion model: Interface trap density Dit ∝ t^0.25 × exp(-Ea/kT).
• Lifetime model: Time to 10% performance loss: τ = A × exp(Ea/kT) × VDD^(-n).
• Compact model for aging: ΔVth(t,T,V) added to SPICE model → simulate aged circuit → verify timing margin after 10 years.

Device Design for Reliability

• Lightly Doped Drain (LDD): Reduces peak field near drain → reduces HCI.
• Halo/pocket implant: Increases Vth uniformity → reduces short-channel effects that worsen HCI.
• Gate oxide engineering: SiON nitridation → reduces H diffusion → reduces NBTI; trade-off with EOT.
• Lower VDD: NBTI ∝ exp(VDD) → reducing VDD from 1.0V to 0.9V → 3–5× NBTI lifetime improvement.

Automotive Reliability Requirements (AEC-Q100)

• Grade 0: -40 to +150°C, 15-year lifetime.
• HTOL (High Temperature Operating Life): 1000 hours at 150°C, 3V stress → must predict 15-year lifetime.
• Accelerated aging: Temperature + voltage acceleration factors → extrapolate from weeks to years.

NBTI and HCI reliability are the transistor aging physics that set the minimum voltage and maximum temperature guardbands in chip design — by knowing that NBTI causes |Vth| to increase ~50mV over a PMOS transistor's 10-year lifetime at junction temperature 125°C, designers add timing guardband to absorb this drift without violating setup time, directly translating the physics of hydrogen diffusion at silicon interfaces into the clock frequency derating and supply voltage headroom that determine product competitiveness over its entire operational lifetime in everything from smartphones to automotive control units.