An NBTI sensor is an on-die reliability monitor that tracks the threshold voltage shift caused by Negative Bias Temperature Instability (NBTI) — the dominant aging mechanism in PMOS transistors that gradually increases $V_{th}$ over time, reducing transistor speed and potentially causing timing failures.

What NBTI Does

• When a PMOS transistor is under negative gate bias (gate at logic 0, which is the "on" state for PMOS), interface traps are generated at the Si/SiO₂ interface.
• These traps increase the PMOS threshold voltage: $\Delta V_{th} \propto t^n$ (where $n \approx 0.16$–0.25 and $t$ is stress time).
• Higher $V_{th}$ → less drive current → slower switching → increased delay.
• NBTI effect accumulates over the chip's lifetime — circuits get progressively slower over years of operation.
• At advanced nodes, NBTI can cause 5–15% speed degradation over 10 years of operation.

Why NBTI Sensors Are Needed

• Designers add guard-band (timing margin) to account for expected NBTI degradation over the chip's lifetime.
• But the actual degradation depends on usage patterns, temperature history, and process variation — the guard-band may be too conservative or too aggressive for any individual chip.
• NBTI sensors provide real-time measurement of the actual degradation — enabling:
• Adaptive Compensation: Adjust voltage or body bias to compensate for measured degradation.
• Lifetime Prediction: Estimate remaining useful life based on degradation trajectory.
• Guard-Band Optimization: Reduce design-time guard-band by relying on runtime monitoring and compensation.

NBTI Sensor Architectures

• Ring Oscillator-Based: A PMOS-dominated ring oscillator whose frequency decreases as NBTI shifts $V_{th}$.
• Stressed vs. Reference: Two identical ROs — one is continuously stressed (always on), the other is periodically de-stressed (used as reference). The frequency difference indicates NBTI degradation.
• Simple and effective — the most common approach.

• $V_{th}$ Extraction Circuit: Directly measures the threshold voltage of a dedicated test transistor.
• More accurate but requires analog circuitry.

• Delay Measurement: Measures the delay increase in a reference logic path due to NBTI.
• Similar to CPM but specifically designed to isolate NBTI-induced delay change.

NBTI Sensor Placement

• Place sensors in regions with PMOS-heavy circuits that experience high stress duty cycles — near clock trees, static logic paths that spend significant time at logic 0.
• Multiple sensors across the die capture spatial variation in NBTI degradation.

NBTI Recovery

• NBTI is partially reversible — when the stress (negative bias) is removed, some of the $V_{th}$ shift recovers.
• AC operation (normal digital switching) already provides partial recovery during each cycle when the gate voltage is high.
• Sensors must account for recovery effects — measurements should be taken consistently to avoid artifacts from recovery.

NBTI sensors are an emerging requirement for mission-critical and long-life applications — they transform aging from an assumed margin penalty into a measured, manageable quantity.