Network-on-Chip (NoC) is the packet-switched communication architecture that replaces traditional shared buses or crossbar switches in complex Systems-on-Chip (SoCs), routing data packets between dozens or hundreds of distributed IP cores (CPUs, GPUs, memory controllers) using routers and scalable network topologies.

What Is Network-on-Chip?

• Definition: A micro-network embedded directly into the silicon, functioning similarly to the Internet, but at the nanometer scale.
• Routers: Intelligent switching nodes placed at intersections that read packet headers and forward flits (flow control units) to the next destination.
• Topologies: The physical arrangement of the network (e.g., 2D Mesh, Ring, Torus, or hierarchical topologies).
• Virtual Channels: Multiple logical buffers sharing a single physical link, preventing routing deadlocks and prioritizing critical traffic (like memory reads).

Why NoC Matters

• Scalability Limit: Traditional shared buses (like early AMBA AHB) collapse under the extreme traffic of 10+ cores; only one device can talk at a time. NoC allows massive parallel communication.
• Wire Delay: In deep submicron nodes, signals cannot cross a large chip in a single clock cycle. NoC uses pipelined links, breaking the journey into multi-cycle manageable lengths.
• Modularity: New IP blocks can be easily attached to the NoC without redesigning global wire routing, massively accelerating SoC design cycles.

Design Tradeoffs

NoC is the fundamental circulatory system of the many-core era — without decentralized packet routing, scaling modern processors past a few cores would immediately choke on their own internal traffic jams.