Network-on-Chip (NoC) Router Design for SoC is the on-chip communication infrastructure that replaces traditional shared-bus architectures with a packet-switched network of routers and links, enabling scalable, high-bandwidth, low-latency data transfer between dozens to hundreds of IP cores in modern systems-on-chip — essential for multi-core processors, AI accelerators, and complex SoCs where bus bandwidth cannot keep pace with the number of communicating agents.

NoC Architecture:

• Topology: the physical arrangement of routers and links determines bandwidth, latency, and area; mesh (2D grid) is most common due to regular structure and VLSI-friendly layout; ring topology suits smaller designs (<16 nodes) with lower area; torus adds wrap-around links to mesh for reduced diameter; hierarchical topologies use clusters of local meshes connected by a global ring or crossbar
• Router Components: each NoC router contains input buffers (FIFOs), a crossbar switch, an arbiter, and routing logic; input buffers store incoming flits (flow control units) pending arbitration; the crossbar connects any input port to any output port; the arbiter resolves contention when multiple inputs request the same output
• Flit-Based Communication: packets are divided into header, body, and tail flits; the header flit contains routing information and requests a path through the network; body flits carry payload data; the tail flit releases resources allocated to the packet at each hop
• Link Design: point-to-point links between adjacent routers use low-swing differential or single-ended signaling; link width (typically 64-256 bits) and frequency determine the per-link bandwidth; repeater insertion manages wire delay for links spanning multiple clock domains

Routing and Arbitration:

• Deterministic Routing: XY routing (dimension-ordered) sends packets first in the X direction, then Y; guarantees deadlock freedom without virtual channels; simple implementation but cannot adapt to congestion
• Adaptive Routing: packets can choose between multiple paths based on link congestion; congestion-aware routing reduces average latency under heavy traffic but requires virtual channels to prevent deadlocks
• Arbitration Policies: round-robin provides fair access among competing flows; priority-based serves critical traffic first; weighted arbitration allocates bandwidth proportionally; age-based policies prevent starvation of low-priority traffic
• Virtual Channels (VCs): multiple independent logical channels share a physical link; VCs prevent head-of-line blocking where a stalled packet in a buffer prevents other packets behind it from proceeding; typically 2-8 VCs per port provide adequate deadlock avoidance and performance

Quality of Service (QoS):

• Traffic Classes: NoC supports multiple traffic classes (e.g., real-time video, best-effort compute, coherency protocol) with differentiated latency and bandwidth guarantees; hardware priority encoding and separate VC allocation per class prevent interference
• Bandwidth Reservation: dedicated bandwidth is allocated to latency-sensitive flows using time-division multiplexing (TDM) or rate-limiting mechanisms; excess bandwidth is shared among best-effort traffic
• Latency Guarantees: worst-case latency bounds are essential for real-time applications; deterministic routing with dedicated VCs and bounded buffer occupancy provides calculable worst-case traversal times

NoC router design is the scalable interconnect solution that enables the continued growth of SoC complexity — providing the structured, analyzable, and high-performance communication fabric that replaces ad-hoc bus architectures with a systematic network approach to on-chip data movement.