Hard Mask is a thin inorganic film used as an etch mask in place of or in addition to photoresist — providing superior etch resistance for deep etches, enabling tighter CD control, and allowing photoresist to be removed without disturbing the pattern below.

Why Hard Masks?

• Photoresist: Poor etch selectivity vs. many materials (SiO2, Si, metals).
• Thick resist needed for etch depth → poor depth-of-focus, wider CD.
• Hard mask: 10–50nm inorganic film → excellent selectivity, thin profile, tight CD.

Common Hard Mask Materials

• Silicon Nitride (Si3N4): Excellent etch selectivity vs. SiO2 and Si. Used for STI, contact, poly gate.
• Silicon Oxide (SiO2): Hard mask for Si etching, TiN gates.
• TiN: Used as hard mask for high-k/metal gate etch, good mechanical hardness.
• SiON: Intermediate properties, doubles as ARC (anti-reflection coating).
• Carbon (a-C): Amorphous carbon — extreme etch resistance, used at 7nm and below.
• SiC or SiCN: Low-k etch stop and hard mask in Cu dual damascene.

Trilayer Hard Mask Stack (< 10nm)

Photoresist (top)
SiON (SHB — spin-on hardmask)
Amorphous Carbon (ACL — bottom anti-reflection + etch mask)
Target material

• Thin resist patterns SOC/SOHM layer.
• SOHM transfers to ACL by O2 plasma (resist gone, ACL patterned).
• ACL transfers pattern to target (ultra-high selectivity).

CD Improvement

• Resist CD ± 3nm — transferred to hard mask by anisotropic etch.
• Hard mask CD ± 1–1.5nm (after etch trim).
• Net CD improvement from resist to final pattern via hard mask.

Process Flow

1. Deposit hard mask. 2. Coat photoresist. 3. Expose and develop resist. 4. Etch hard mask (opens pattern in hard mask). 5. Strip resist (O2 plasma — hard mask survives). 6. Etch target layer using hard mask. 7. Strip hard mask (selective to target).

Hard mask technology is the enabler of deep, aggressive etches in advanced CMOS — without hard masks, the sub-5nm features and high-aspect-ratio contacts of modern transistors would be impossible to pattern reliably.