Silicon Nitride in CMOS Process Integration is the versatile dielectric material used in multiple roles throughout the transistor fabrication flow — as a hardmask to protect gate electrodes during etch, as a spacer dielectric to define source/drain positioning, as a stress liner to engineer channel strain, as an etch stop layer in contact and via etch, and as a passivation layer — with silicon nitride's unique combination of mechanical hardness, chemical resistance to HF and TMAH, adjustable stress (tensile to compressive depending on deposition conditions), and compatibility with selective etch chemistries making it uniquely suited for these distinct applications within the same process flow.

SiN Material Properties

SiN as Gate Hardmask (Gate Cap)

• After gate poly deposition: LPCVD SiN deposited → hardmask for gate etch.
• Provides: High etch selectivity (poly:SiN = 15:1) → SiN survives gate poly etch.
• In RMG process: SiN cap remains on dummy poly → CMP planarizes ILD to SiN level (POC) → SiN exposed → dummy poly removal selective to SiN.
• Selective removal: H₃PO₄ (85%, 160°C) → etches SiN at 6 nm/min, SiO₂ at < 0.2 nm/min → 30:1 SiN:SiO₂ selectivity.

SiN Spacer for S/D Placement

• Thin spacer (2–5 nm SiO₂) → offset implant (LDD/extension implant).
• Thick spacer (8–20 nm SiN) → main S/D implant → S/D junction under spacer edge.
• Spacer formation: Blanket PECVD SiN → anisotropic etch (removes flat surfaces, leaves sidewalls).
• Spacer thickness precision: ±0.5 nm → determines S/D junction position → Vth and SCE impact.
• Inner spacer (GAA nanosheet): SiON or SiCO → between nanosheets → prevents gate/S/D short.

Tensile SiN Stress Liner (NMOS)

• High-tensile LPCVD SiN (σ = +1.2 GPa) deposited over NMOS region after S/D silicidation.
• Tensile film → transfers tensile stress to Si channel below → increases electron mobility 10–20%.
• Selective deposition or patterned mask: Remove over PMOS (tensile stress hurts holes).
• Or: Dual-stress liner: Tensile SiN over NMOS, compressive SiN over PMOS → optimize both.

Compressive SiN (PECVD) for PMOS

• PECVD SiN with high RF power → compressive stress (-1 to -2 GPa).
• Deposited over PMOS → transfers compressive stress to channel → hole mobility increase 10–15%.
• Trade-off: Compressive SiN = high H content → NBTI concern → optimize to balance stress vs reliability.

SiN as Etch Stop Layer

• Contact etch: SiO₂ ILD etched with C₄F₈/Ar → high selectivity to SiN (SiO₂:SiN ≈ 30:1 in typical recipe).
• SiN contact etch stop: Thin SiN (10–20 nm) above active → contact etch stops on SiN → additional timed etch → open contact → protects underlying Si.
• Self-aligned contact: SiN capping gate sidewalls → contact misalignment → SiN prevents short to gate.

SiN Passivation

• Final passivation layer: PECVD SiN 500–1000 nm → protects chip from moisture, ion contamination.
• SiN is impermeable to Na, K ions → prevents contamination-induced Vth shift in field.
• Also: SiN laser hard enough for probe → mechanical protection during bond pad probing.

SiN Etch Selectivity Summary

Silicon nitride in CMOS is the Swiss-army material of semiconductor process integration — no other single dielectric serves simultaneously as gate hardmask, spacer, etch stop, stress liner, and final passivation with such process compatibility across the wide temperature range from 350°C PECVD to 750°C LPCVD, and its unique wet etch reversal (etches in H₃PO₄ but resists HF while SiO₂ is opposite) provides the chemical selectivity toolkit that enables dozens of critical process steps where two adjacent films must be selectively processed without affecting each other, making SiN an indispensable enabler of modern transistor architecture complexity.