Home Knowledge Base NUMA Architecture and Optimization

NUMA Architecture and Optimization is the multi-processor memory architecture where each processor socket has locally attached memory that it can access faster (50-100 ns) than remote memory attached to another socket (100-200 ns) — creating a non-uniform memory access pattern that requires NUMA-aware software design to ensure that threads access local memory wherever possible, because naive memory allocation can cause 30-50% performance degradation when data is consistently fetched from remote NUMA nodes.

NUMA Hardware Structure

A 2-socket server with 64 cores per socket:

NUMA Ratio: Remote/Local latency ratio. Typical: 1.5-2.5x. Higher ratios demand more aggressive NUMA optimization. AMD EPYC's chiplet architecture creates multiple NUMA domains (NPS — NUMA Nodes Per Socket) within a single socket.

Memory Allocation Policies

Linux NUMA policies (set via numactl, mbind(), set_mempolicy()):

NUMA-Aware Programming

NUMA in Practice

NUMA Architecture is the unavoidable physical reality of multi-socket computing — where the speed of light and electrical signal propagation create inherent latency asymmetry that software must acknowledge and accommodate, turning memory placement and thread affinity into first-class performance optimization concerns.

numa architecturenon uniform memory accessnuma aware schedulingmemory affinity numasocket memory topology

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