Home Knowledge Base Network-on-Chip (NoC)

Network-on-Chip (NoC) is the scalable on-chip communication infrastructure that replaces traditional bus and crossbar interconnects in complex SoCs — using packet-switched routing through a network of on-chip routers connected in mesh, ring, or tree topologies to provide high-bandwidth, low-latency communication between dozens to hundreds of IP blocks while maintaining manageable wiring complexity and design modularity.

Why NoC Replaced Buses

Traditional shared buses (AMBA AHB) don't scale beyond ~10 masters — arbitration latency grows linearly with masters, and the shared medium creates a bandwidth bottleneck. Crossbars (AMBA AXI with NIC-400) scale better but wiring grows as O(N²), becoming impractical beyond ~20 ports. NoC provides O(N) wiring growth with O(N) aggregate bandwidth, scaling to 100+ endpoints.

NoC Architecture

Topologies

Flow Control

Quality of Service (QoS)

SoCs have mixed traffic — latency-critical (CPU cache misses, display refresh) and bandwidth-intensive (DMA, video codec). NoC QoS mechanisms (priority-based arbitration, bandwidth reservation, virtual channels per traffic class) ensure real-time deadlines are met despite background traffic.

Network-on-Chip is the communication backbone of modern SoC design — providing the scalable, modular interconnect fabric that enables hundreds of IP blocks to communicate efficiently while keeping physical design complexity manageable.

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