Optical Proximity Correction (OPC) is the computational lithography technique that systematically modifies the photomask pattern to pre-compensate for the optical and process distortions that occur during wafer exposure — adding sub-resolution assist features (SRAFs), biasing line widths, moving edge segments, and reshaping corners so that the pattern actually printed on the wafer matches the intended design, despite the diffraction, aberration, and resist effects that would otherwise distort it.
Why the Mask Pattern Cannot Equal the Design
At feature sizes near and below the wavelength of light (193 nm for ArF, 13.5 nm for EUV), diffraction causes the aerial image to differ significantly from the mask pattern:
- Isolated lines print wider than dense lines at the same design width (iso-dense bias).
- Line ends shorten (pull-back) due to diffraction and resist effects.
- Corners round because the high-spatial-frequency information required to print sharp corners is lost beyond the lens numerical aperture cutoff.
- Neighboring features influence each other — a line adjacent to an open space prints differently than the same line in a dense array.
OPC Approaches
- Rule-Based OPC: Simple geometry-dependent corrections. Example: add 5 nm of bias to isolated lines, add serif (square bump) to outer corners, subtract serif from inner corners. Fast computation but limited accuracy for complex interactions.
- Model-Based OPC (MBOPC): A full physical model of the optical system (aerial image) and resist process is used to simulate what each mask edge prints on the wafer. An iterative optimization loop adjusts each edge segment (there may be 10¹⁰-10¹¹ edges on a full chip mask) until the simulated wafer pattern matches the design target within tolerance. This is the production standard at all advanced nodes.
- Inverse Lithography Technology (ILT): Instead of iteratively adjusting edges, ILT formulates the mask pattern calculation as a mathematical inverse problem — directly computing the mask shape that produces the desired wafer image. ILT-generated masks have free-form curvilinear shapes that provide larger process windows than MBOPC. Previously too computationally expensive for full-chip application, ILT is now becoming production-feasible with GPU-accelerated computation.
Sub-Resolution Assist Features (SRAFs)
Small, non-printing features placed near the main pattern on the mask. SRAFs modify the local diffraction pattern to improve the process window of the main features. SRAF width is below the printing threshold (~0.3 × wavelength/NA), so they assist the aerial image without creating unwanted features on the wafer.
Computational Scale
Full-chip MBOPC for a single mask layer requires evaluating 10¹⁰-10¹¹ edge segments through 10-50 iterations of electromagnetic simulation, resist modeling, and edge adjustment. Run time: 12-48 hours on a cluster of 1000+ CPU cores. OPC computation is one of the largest computational workloads in the semiconductor industry.
OPC is the computational intelligence that bridges the gap between design intent and physical reality — transforming the photomask from a literal copy of the design into a pre-distorted pattern that, after passing through the imperfect physics of lithography, produces exactly the features the designer intended.