Optical Proximity Correction (OPC) and Resolution Enhancement Techniques (RET) are the computational lithography methods that pre-distort photomask patterns to compensate for optical diffraction, interference, and resist chemistry effects — ensuring that features printed on the wafer accurately match the intended design dimensions despite the fact that the lithography wavelength (193 nm ArF, 13.5 nm EUV) is comparable to or larger than the features being printed (10–100 nm). Without OPC, critical features would round, shrink, or fail to print entirely.

The Optical Proximity Problem

• At sub-wavelength lithography, diffraction causes light from adjacent features to interfere.
• Isolated lines print at different dimensions than dense arrays (proximity effect).
• Line ends pull back (end shortening); corners round; small features may not resolve.
• OPC modifies the mask to pre-compensate these systematic distortions.

OPC Techniques

1. Rule-Based OPC (Simple)

• Apply fixed geometric corrections based on design rules: add serifs to corners, extend line ends, bias isolated vs. dense features.
• Fast, deterministic; used for non-critical layers or as starting point.

2. Model-Based OPC

• Uses physics-based model of optical imaging + resist chemistry to predict printed contour for any mask shape.
• Iterative: adjust mask fragments → simulate aerial image → compare to target → adjust again.
• Achieves ±1–2 nm accuracy on printed features.
• Runtime: Hours to days for full chip on modern EUV nodes → requires large compute clusters.

3. SRAF (Sub-Resolution Assist Features)

• Insert small features near isolated main features that don't print themselves but improve depth of focus and CD uniformity.
• Assist features scatter light constructively to improve process window of the main feature.
• Placement rules: SRAF must be smaller than resolution limit; cannot merge with main feature.
• Model-based SRAF placement (MBSRAF) more accurate than rule-based.

4. ILT (Inverse Lithography Technology)

• Mathematically inverts the imaging equation to compute the theoretically optimal mask for a target pattern.
• Produces highly non-Manhattan, curvilinear mask shapes → maximum process window.
• Curvilinear masks require e-beam mask writers (MBMW) — multi-beam machines that can write arbitrary curves.
• Used for critical EUV layers at 3nm and below.

5. Source-Mask Optimization (SMO)

• Simultaneously optimize the illumination source shape AND mask pattern for maximum process window.
• Source shape (e.g., dipole, quadrupole, freeform) tuned with programmable illuminators (FlexRay, Flexwave).
• SMO + ILT = full computational lithography for critical layers.

OPC Workflow

Design GDS → Flatten → OPC engine (model-based)
                              ↓
              Fragment edges → Simulate aerial image
                              ↓
              Compare to target → compute edge placement error (EPE)
                              ↓
              Move mask edge fragments → re-simulate
                              ↓
              Converge (EPE < 1 nm) → OPC GDS output
                              ↓
              Mask write (MBMW for curvilinear ILT)

Process Window

• OPC is measured by process window: the range of focus and exposure that keeps CD within spec.
• Larger process window → more manufacturing margin → better yield.
• SRAF + ILT can improve depth of focus by 30–50% vs. uncorrected mask.

EUV OPC Specifics

• EUV has 3D mask effects: absorber is thick (60–80 nm) relative to wavelength → shadowing effects.
• EUV OPC must include 3D mask model (vs. thin-mask approximation used for ArF).
• Stochastic effects: EUV has lower photon count per feature → shot noise → local CD variation.
• OPC must account for stochastic CD variation in resist to avoid edge placement errors.

OPC and RET are the computational foundation that extends optical lithography beyond its apparent physical limits — by treating mask design as an inverse optics problem and applying massive computational resources to solve it, modern OPC enables 193nm light to print 10nm features and EUV to print 8nm half-pitch patterns, making computational lithography as important to chip manufacturing as the stepper hardware itself.