Overlay is the layer-to-layer alignment accuracy of a chip — how precisely the pattern printed at one lithography step lands on the patterns already on the wafer. A chip is built from dozens of patterned layers that must register to one another within a few nanometers: a via has to land on the metal pad beneath it, a gate has to sit between its source and drain. Overlay is the metric for that registration, alignment is the act of achieving it, and overlay error is the residual misalignment left behind. At leading nodes the overlay budget has shrunk to low single-digit nanometers, making it one of the hardest constraints in manufacturing and a core competence of the scanner (ASML) and metrology (KLA) toolmakers.\n\nOverlay is a displacement field, measured with dedicated targets. The misregistration between two layers is not a single number but a vector — a (dx, dy) displacement — that varies across the wafer and across each exposure field. It is measured on purpose-built overlay targets (box-in-box, or grating-based AIM and µDBO marks) placed in the scribe lines between dies, where a metrology tool reads the offset between the lower-layer and upper-layer features. From many such sites the tool builds a map of overlay across the whole wafer, and that map is the raw signal the alignment and correction system works from. When overlay drifts, features from adjacent layers stop lining up — a via lands partly off its pad, giving an open or a high-resistance contact, or bridges to a neighbour.\n\nAlignment corrects overlay by modeling it as translation, rotation, magnification, and higher-order terms. Before each exposure the scanner measures alignment marks on the incoming wafer and fits the overlay field to a model: rigid translation and rotation of the wafer, symmetric and asymmetric magnification (the wafer or field slightly scaled), and increasingly high-order and per-field corrections that capture the non-linear distortion left by prior processing, wafer chucking, and thermal effects. The scanner then applies these corrections in real time — shifting, rotating, and warping the exposure grid — to drive the residual overlay toward zero. Run-to-run feedback (advanced process control) folds each lot's measured overlay back into the next, and modern flows correct at fine spatial granularity because the distortions are no longer simple.\n\n| Concept | Meaning | Why it matters |\n|---|---|---|\n| Overlay | layer-to-layer registration (dx, dy) | vias land on pads |\n| Overlay error | residual misalignment | opens, shorts, yield loss |\n| Alignment marks | scanner-read fiducials | input to the correction model |\n| Overlay targets | box-in-box / AIM in scribe | how overlay is measured |\n| Correction model | translation, rotation, mag, high-order | nulls the overlay field |\n| EPE | printed edge vs intended | overlay is a top contributor |\n\n``svg\n\n``\n\nOverlay is a dominant term in the edge-placement-error budget, and multi-patterning multiplies it. The ultimate quantity that must be controlled is edge placement error (EPE) — how far a printed edge sits from its intended position relative to the other layers — and overlay is one of its largest contributors alongside critical-dimension variation. This coupling is why overlay matters so much at advanced nodes: when a layer is built from multiple exposures (LELE multi-patterning), the spacing between features is set by overlay directly, so a few nanometers of misalignment turn into pitch variation and yield loss. Tightening overlay therefore pays off twice — better layer-to-layer registration and a wider process window for multi-patterned layers — which is why every scanner generation spends heavily on alignment sensors, wafer-stage accuracy, and correction models.\n\nRead overlay through a quant lens rather than a 'line the layers up' lens: it is a two-dimensional displacement field over the wafer that alignment tries to null by fitting and subtracting a model — translation and rotation first, then magnification, then higher-order and per-field terms as the residual demands. The number that matters is the residual after correction, and it feeds straight into the edge-placement-error budget that decides whether a via lands on its pad. Every nanometer clawed back from overlay is a nanometer returned to CD or pitch margin, which is why at leading nodes overlay control — not just resolution — is often the real limiter on how tight a design rule can be.