Overlay metrology measures the in-plane registration vector between a newly patterned lithography layer and a reference layer already on the wafer. A tool observes dedicated targets or qualified device-like structures at many wafer and field locations, then fits the measured x- and y-offset field to correction models used by the scanner and process-control system. The number is never just “scanner alignment”: reticle writing and placement, wafer alignment, stage and lens behavior, wafer deformation, film stress, etch or CMP asymmetry, target design, and metrology bias can all contribute. Golden overlay control therefore requires three separations—true pattern-placement error from measurement bias, correctable systematic signatures from residual error, and convenient target overlay from the on-product registration that actually affects yield.

Image-based overlay locates the relative centers of two target layers in an optical image, but precision alone does not establish accuracy. Frame-in-frame, bar-in-bar, and segmented imaging targets are mature and visually interpretable. Optical-path or field-of-view asymmetry can create tool-induced shift (TIS), while asymmetric target formation from etch, deposition, CMP, resist profile, or film stack can create wafer- or process-induced shift. Repeating a biased target reduces random noise but preserves the bias, so target reversal or 180-degree orientation measurements, traceable overlay artifacts, focus and wavelength splits, and cross-tool matching are used to characterize the measurement system under a specified recipe.

Diffraction-based overlay infers displacement from the asymmetry of diffracted orders generated by stacked gratings, trading resolved edges for a model-sensitive optical signal. DBO can deliver high precision and small targets, but it is not automatically more accurate than IBO: bottom-grating asymmetry, sidewall differences, film thickness, focus, wavelength, polarization, and target design can convert process variation into apparent overlay. Multiple intentionally biased gratings are commonly used to calibrate signal versus displacement, and recipe robustness is tested across process splits. Agreement between IBO, DBO, and device-based reference measurements is useful evidence, but disagreement must be investigated rather than resolved by assuming one technology is intrinsically correct.

TIS correction is a measurement-system calibration, not permission to subtract every disagreement as a tool constant. Under target-reversal assumptions, measurements before and after a 180-degree rotation separate components that rotate with the artifact from components fixed in the instrument frame. A traceable standard can establish scale and check accuracy, while control wafers monitor stability. Target asymmetry can violate the simple separation and produce wavelength-, focus-, or orientation-dependent wafer-induced shift, so a correction is valid only for the qualified target, stack, recipe, and tool state; hardware service, illumination changes, algorithm revisions, or a new target design trigger requalification.

A first-order overlay model is a vector field, not a root-sum-square of scanner, reticle, process, and metrology labels. At wafer or field position $(x,y)$, one useful affine form is

where $T_x,T_y$ describe translation, $R$ rotation, $M_x,M_y$ magnification-like terms, and $\mathbf r$ contains orthogonality, trapezoid, higher-order scanner or wafer signatures, process deformation, and noise not captured by the first-order model. Fitted coefficients can be fed forward or back only to actuators capable of correcting the corresponding signature. Measurement uncertainty is evaluated separately—with bias, repeatability, reproducibility, sampling, and model residuals treated according to their correlation—rather than automatically adding every contributor in quadrature.

Design overlay targets for the current layer pair, considering IBO and/or DBO measurement requirements → Print the current resist layer and expose the overlay targets alongside device features → Measure overlay using the qualified metrology mode (IBO, DBO, or both) across the sampling plan → Correct raw measurements for characterized tool-induced shift using the established calibration → Decompose the corrected overlay error into translation, rotation, and magnification components → Compare each component against its allocated portion of the overlay error budget → Feed translation and rotation corrections back into the scanner's exposure recipe for subsequent lots → Investigate any component exceeding budget by isolating scanner, reticle, or process contribution → Cross-check IBO and DBO results against each other where both are available to rule out technique-specific artifacts → Periodically verify on-product overlay against scribe-line target overlay to confirm target-based measurement remains representative of true device registration

Sampling plan design trades measurement time against the risk of missing a spatially localized overlay excursion, because overlay error can vary across a wafer and even across a single exposure field rather than being a single uniform number. A sparse sampling plan measuring only a handful of sites per wafer runs faster but risks missing field-edge or wafer-edge-specific overlay signatures that a denser plan would catch, while a dense plan that measures many sites per field and many fields per wafer characterizes higher-order distortion more completely at the cost of metrology tool time that could otherwise support other measurements; production sampling plans are typically tuned empirically, starting dense during process qualification to characterize the full spatial signature and thinning to the minimum sampling that still reliably catches known excursion modes once the process is stable.

On-product overlay measurement — assessing registration using actual device structures rather than dedicated scribe-line targets — has grown in importance because scribe-line targets, however carefully designed, do not always experience identical process conditions to the dense in-die patterns whose registration actually determines device yield. Differences in local pattern density, proximity effects during etch or CMP, and even subtle differences in how scribe-line versus in-die resist patterns respond to processing can cause scribe-line-measured overlay to diverge from the overlay that actually exists on the product structures that matter for yield, so on-product or in-die overlay measurement, despite its greater technical difficulty, has become necessary at advanced nodes specifically to close this representativeness gap between what a convenient scribe-line target reports and what the device itself actually experiences.

Read overlay metrology through an error-budget-decomposition lens: each reported vector combines pattern placement, process-distorted targets, sampling and model choices, and measurement uncertainty; control improves only when those terms are separated well enough to correct the scanner, repair the process, redesign the target, or recalibrate the metrology system for the right reason.