Oxidation Simulation is the TCAD (Technology Computer-Aided Design) computational modeling of silicon dioxide (SiO₂) growth kinetics during thermal oxidation — predicting the thickness, growth rate, stress distribution, and interface geometry of oxide layers based on the Deal-Grove model and its extensions, enabling semiconductor process engineers to design gate oxide, field oxide, and STI (Shallow Trench Isolation) processes without the time and cost of empirical wafer experiments.
What Is Oxidation Simulation?
Thermal oxidation converts silicon to silicon dioxide by exposing the wafer to O₂ or H₂O at 700–1200°C. The chemical reaction consumes silicon and grows oxide in both directions — partial oxide growth into the original silicon surface, partial oxide growth outward. Simulation predicts all aspects of this process:
The Deal-Grove Model (1965)
The foundational oxidation model describes a linear-parabolic growth law:
x² + Ax = B(t + τ)
Where x = oxide thickness, t = time, τ = initial offset, A = linear rate constant, B = parabolic rate constant. The model captures two transport-limited regimes:
- Linear Regime (thin oxides): Growth rate limited by the reaction at the Si/SiO₂ interface — rate proportional to oxidant concentration at the interface.
- Parabolic Regime (thick oxides): Growth rate limited by oxidant diffusion through the existing oxide layer — rate slows as the oxide thickens.
Model Extensions
- Massoud Model: For oxides thinner than ~20 nm, the actual growth rate is significantly faster than Deal-Grove predicts. An empirical correction term accounts for the "thin oxide enhancement effect," important for gate oxide and tunnel oxide simulation.
- Viscoelastic Model: Silicon dioxide flows like a viscous material at oxidation temperatures while the underlying silicon is rigid. This viscous flow generates and relieves stress, which in turn affects oxidant diffusivity and reaction rates. Critical for modeling bird's beak formation in LOCOS isolation and stress in STI corners.
- 2D/3D Geometric Models: Oxidation consumes silicon (~46% of oxide thickness) while expanding outward (~54% outward), causing complex interface shape evolution at mask edges, trench corners, and fin structures. Level set and volume-of-fluid methods track the moving Si/SiO₂ interface in 2D and 3D.
Why Oxidation Simulation Matters
- Gate Oxide Precision: MOSFET threshold voltage depends directly on gate oxide thickness (tox) through Vth ∝ 1/Cox ∝ tox. For 1.5 nm SiO₂ gate oxides in modern devices, 0.1 nm thickness variation changes Vth by hundreds of millivolts — simulation-guided process control is essential.
- Stress Management: Oxidation volume expansion (~2.2× volume increase from Si to SiO₂) generates gigapascal-scale compressive stress at mask edges and trench corners. Uncontrolled stress causes silicon crystal dislocations that degrade junction leakage and device reliability.
- STI Corner Optimization: Shallow Trench Isolation corners where oxide meets silicon are stress concentration points. Oxidation simulation guides the liner oxidation step that rounds these corners, preventing electric field enhancement and oxide breakdown.
- FinFET Oxidation: In FinFET structures, oxidation of narrow silicon fins (5–10 nm wide) saturates as oxidant cannot easily reach the fin core. Simulation predicts fin shrinkage, stress buildup, and the point at which continued oxidation converts the entire fin to oxide — a critical process window.
- Rapid Thermal Oxidation: Short, high-temperature oxidation cycles used in advanced nodes require accurate transient models that capture the initial enhanced growth before steady-state kinetics dominate.
Tools
- Synopsys Sentaurus Process: Industry-standard TCAD with full Deal-Grove + Massoud + viscoelastic oxidation models and 3D geometric tracking.
- Silvaco ATHENA: TCAD oxidation simulation with 2D/3D capabilities.
- SUPREM-IV (Stanford University Process Engineering Model): The academic predecessor that established the modeling foundations used in commercial tools.
Oxidation Simulation is predicting the controlled rusting of silicon — mathematically modeling how oxygen consumes and transforms silicon into insulating glass at atomic precision, enabling engineers to design the nanometer-scale oxide layers that define transistor characteristics before committing to expensive wafer fabrication runs.