Package-on-Package (PoP) is the 3D packaging configuration that stacks a memory package (LPDDR DRAM) directly on top of a processor package (SoC/AP), connecting them through a standardized set of solder balls or copper pillars that mate at the package boundary — achieving the closest possible physical proximity between processor and memory while maintaining independent supply chains, testability, and repairability for each package. PoP is the dominant packaging architecture for mobile application processors in smartphones and tablets.
PoP Structure
``
┌─────────────────────────┐
│ Memory Package (top) │ ← LPDDR4X/5 DRAM
│ (FBGA, 400–800 balls) │
└────────┬────────────────┘
│ Interface balls (100–400, 0.4–0.5 mm pitch)
┌────────┴────────────────┐
│ Logic Package (bottom) │ ← AP/SoC
│ (FCBGA on substrate) │
└─────────────────────────┘
│ PCB balls
┌─────────────────────────┐
│ PCB / Motherboard │
└─────────────────────────┘
Why PoP for Mobile
- Proximity: Memory is 0.3–0.5 mm above the processor → wire length reduced vs. side-by-side → lower latency, lower power.
- Supply chain independence: Memory and processor sourced, tested, and qualified independently → mix and match from different vendors.
- Rework: Failed bottom package can be replaced without discarding top memory (vs. integrated solutions).
- Standardization: JEDEC and SSWG (PoP Standardization Working Group) define interface geometry → interoperability across vendors.
PoP Interface
- Interface balls: Solder balls on underside of top package mate with pads on top surface of bottom package.
- Pitch: 0.4–0.5 mm for standard PoP; 0.35 mm for advanced PoP.
- Ball count: 100–600 depending on memory bandwidth requirements.
- Through-mold via (TMV): Via drilled or laser-formed through the mold compound of bottom package → allows interface balls on top surface without affecting logic die routing.
Through-Mold Via (TMV) Process
`
1. Logic die flip-chip attached to substrate
2. Underfill + mold compound encapsulation
3. Laser drill vias through mold (500–600 µm diameter)
4. Cu plating or solder fill of vias → create top-surface pads
5. Interface solder balls mounted on TMV pads
6. Top memory package placed + reflow
PoP Generations in Mobile
| Generation | Node | Memory | Interface Pitch | Package Thickness |
|-----------|------|--------|----------------|------------------|
| PoP 1st gen | 45nm | LPDDR2 | 0.65 mm | 1.4 mm |
| PoP 2nd gen | 28nm | LPDDR3 | 0.5 mm | 1.2 mm |
| PoP 3rd gen | 16nm FinFET | LPDDR4 | 0.4 mm | 1.0 mm |
| Advanced PoP | 5nm | LPDDR5 | 0.35 mm | 0.9 mm |
Key Users and Products
- Apple: A-series chips (A14, A15, A16) use TSMC InFO_PoP — LPDDR4X memory PoP stacked on SoC.
- Qualcomm: Snapdragon series uses PoP with LPDDR5 from Samsung/Micron/SK Hynix.
- MediaTek: Dimensity series uses PoP architecture.
- Samsung Exynos: Galaxy SoCs use PoP with Samsung LPDDR5.
PoP vs. Alternatives
| Architecture | Bandwidth | Power | Cost | Integration |
|-------------|----------|-------|------|-------------|
| PoP | 50–85 GB/s (LPDDR5) | Good | Low | Proven, standard |
| CoWoS (HBM) | 1+ TB/s | Best | Very high | HPC/AI only |
| SiP (same substrate) | 50–85 GB/s | Good | Medium | Limited rework |
| On-die SRAM | 5–10 TB/s | Excellent | Die area cost | Cache only |
PoP is the packaging architecture that makes smartphones possible within a millimeter of board space — by stacking processor and memory into a compact, standardized interface that balances performance, cost, and supply chain flexibility, PoP has been the mobile semiconductor industry's workhorse packaging solution for over 15 years and continues to evolve with each new processor and DRAM generation.