Package substrate is the multilayer organic interconnect structure inside a BGA or flip-chip package that bridges the fine-pitch bumps on a silicon die to the coarser solder balls that connect to the printed circuit board. It performs pitch fan-out, signal routing, power distribution, and mechanical support, and in advanced packages it is the dominant cost driver and the limiting factor for bandwidth density.

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  <text x="380" y="22" fill="#e6edf3" font-size="13" font-weight="700" text-anchor="middle">Package Substrate</text>
  <text x="380" y="36" fill="#8b98a5" font-size="10" text-anchor="middle">multilayer organic interconnect bridging fine die bumps to coarse PCB solder balls — the integration backbone of every BGA</text>

  <!-- ── PANEL 1: BGA substrate cross-section ── -->
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  <text x="126" y="58" fill="#93c5fd" font-size="10" font-weight="700" text-anchor="middle">Flip-Chip BGA Cross-Section</text>

  <!-- Die on top -->
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  <text x="118" y="84" fill="#86efac" font-size="9.5" font-weight="700" text-anchor="middle">Silicon Die</text>

  <!-- C4 bumps -->
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  <ellipse cx="85" cy="96" rx="7" ry="5" fill="#b45309" stroke="#fbbf24" stroke-width="0.8"/>
  <ellipse cx="108" cy="96" rx="7" ry="5" fill="#b45309" stroke="#fbbf24" stroke-width="0.8"/>
  <ellipse cx="131" cy="96" rx="7" ry="5" fill="#b45309" stroke="#fbbf24" stroke-width="0.8"/>
  <ellipse cx="154" cy="96" rx="7" ry="5" fill="#b45309" stroke="#fbbf24" stroke-width="0.8"/>
  <ellipse cx="177" cy="96" rx="7" ry="5" fill="#b45309" stroke="#fbbf24" stroke-width="0.8"/>
  <text x="232" y="98" fill="#fbbf24" font-size="8" text-anchor="end">C4 bumps</text>
  <text x="232" y="107" fill="#6b7280" font-size="7.5" text-anchor="end">80-150 µm pitch</text>

  <!-- Substrate build-up layers -->
  <!-- Top RDL layer 1 -->
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  <text x="16" y="109" fill="#60a5fa" font-size="7.5">L1</text>
  <!-- trace lines in L1 -->
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  <line x1="100" y1="103" x2="140" y2="103" stroke="#60a5fa" stroke-width="1.5"/>
  <line x1="155" y1="103" x2="195" y2="103" stroke="#60a5fa" stroke-width="1.5"/>

  <!-- vias between L1 and L2 -->
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  <line x1="120" y1="112" x2="120" y2="120" stroke="#fbbf24" stroke-width="1.5"/>
  <line x1="175" y1="112" x2="175" y2="120" stroke="#fbbf24" stroke-width="1.5"/>

  <!-- L2 -->
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  <text x="16" y="129" fill="#60a5fa" font-size="7.5">L2</text>
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  <line x1="140" y1="123" x2="200" y2="123" stroke="#60a5fa" stroke-width="1.5"/>

  <!-- Core -->
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  <text x="118" y="147" fill="#94a3b8" font-size="8.5" text-anchor="middle">Glass/PP Core (0.1-0.4 mm)</text>
  <!-- core via (PTH) -->
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  <text x="118" y="163" fill="#6b7280" font-size="7.5" text-anchor="middle">PTH via</text>

  <!-- L3 (bottom) -->
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  <text x="16" y="163" fill="#60a5fa" font-size="7.5">L3</text>

  <!-- vias to L4 -->
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  <line x1="145" y1="166" x2="145" y2="174" stroke="#fbbf24" stroke-width="1.5"/>

  <!-- L4 -->
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  <text x="16" y="183" fill="#60a5fa" font-size="7.5">L4</text>
  <text x="232" y="180" fill="#60a5fa" font-size="7.5" text-anchor="end">ABF</text>
  <text x="232" y="189" fill="#6b7280" font-size="7.5" text-anchor="end">build-up</text>

  <!-- Solder resist -->
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  <text x="16" y="193" fill="#4ade80" font-size="7.5">SR</text>

  <!-- BGA solder balls -->
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  <ellipse cx="85" cy="202" rx="9" ry="6" fill="#7c3aed" stroke="#c4b5fd" stroke-width="0.8"/>
  <ellipse cx="115" cy="202" rx="9" ry="6" fill="#7c3aed" stroke="#c4b5fd" stroke-width="0.8"/>
  <ellipse cx="145" cy="202" rx="9" ry="6" fill="#7c3aed" stroke="#c4b5fd" stroke-width="0.8"/>
  <ellipse cx="175" cy="202" rx="9" ry="6" fill="#7c3aed" stroke="#c4b5fd" stroke-width="0.8"/>
  <text x="232" y="204" fill="#c4b5fd" font-size="8" text-anchor="end">BGA balls</text>
  <text x="232" y="213" fill="#6b7280" font-size="7.5" text-anchor="end">0.8-1.0 mm pitch</text>

  <text x="118" y="230" fill="#6b7280" font-size="8" text-anchor="middle">fan-out: 150 µm pitch → 1000 µm pitch</text>
  <text x="118" y="241" fill="#6b7280" font-size="8" text-anchor="middle">4-16 signal layers + 2+ power planes</text>

  <!-- ── PANEL 2: Advanced packaging evolution ── -->
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  <text x="378" y="58" fill="#fcd34d" font-size="10" font-weight="700" text-anchor="middle">Advanced Packaging Hierarchy</text>

  <!-- Organic BGA -->
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  <text x="360" y="76" fill="#fcd34d" font-size="9" font-weight="700">Organic BGA substrate</text>
  <text x="262" y="76" fill="#fbbf24" font-size="7.5" font-weight="600">  </text>
  <text x="378" y="86" fill="#94a3b8" font-size="8" text-anchor="middle">ABF build-up · 4-16 layers · ~1-2 mm/s trace width · mature</text>

  <!-- EMIB -->
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  <text x="378" y="110" fill="#93c5fd" font-size="9" font-weight="700" text-anchor="middle">EMIB (Intel) — embedded bridge die</text>
  <text x="378" y="120" fill="#94a3b8" font-size="8" text-anchor="middle">Si bridge in organic substrate · 55 µm bump pitch · HBM+CPU</text>

  <!-- CoWoS -->
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  <text x="378" y="144" fill="#6ee7b7" font-size="9" font-weight="700" text-anchor="middle">CoWoS (TSMC) — Si interposer</text>
  <text x="378" y="154" fill="#94a3b8" font-size="8" text-anchor="middle">2.5D Si interposer · &lt;10 µm RDL · GPU+HBM · high cost</text>

  <!-- SoIC / hybrid bond -->
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  <text x="378" y="178" fill="#c4b5fd" font-size="9" font-weight="700" text-anchor="middle">SoIC / Hybrid Bond (TSMC/Samsung)</text>
  <text x="378" y="188" fill="#94a3b8" font-size="8" text-anchor="middle">3D face-to-face Cu-Cu bond · &lt;1 µm pitch · no substrate between</text>

  <!-- Pitch annotation -->
  <text x="262" y="206" fill="#64748b" font-size="8.5">Bump pitch evolution:</text>
  <text x="262" y="217" fill="#fbbf24" font-size="8">C4: 150 µm →</text>
  <text x="340" y="217" fill="#60a5fa" font-size="8">µbump: 40 µm →</text>
  <text x="420" y="217" fill="#c4b5fd" font-size="8">hybrid: &lt;1 µm</text>
  <text x="262" y="228" fill="#64748b" font-size="8">Each step: higher bandwidth, shorter wire, lower power/bit</text>
  <text x="262" y="240" fill="#64748b" font-size="8">Organic substrate sits under every tier as the board interface</text>

  <!-- ── PANEL 3: ABF material + key specs ── -->
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  <text x="632" y="58" fill="#6ee7b7" font-size="10" font-weight="700" text-anchor="middle">ABF &amp; Substrate Specs</text>

  <!-- ABF layer breakdown -->
  <text x="522" y="72" fill="#94a3b8" font-size="9" font-weight="600">Ajinomoto Build-up Film (ABF) layers:</text>
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  <text x="632" y="88" fill="#6ee7b7" font-size="8.5" text-anchor="middle">Epoxy resin dielectric (Er 3.0-3.5)</text>
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  <text x="632" y="106" fill="#93c5fd" font-size="8.5" text-anchor="middle">Cu seed + electrolytic Cu traces (SAP process)</text>
  <rect x="522" y="112" width="220" height="16" rx="3" fill="#1a2e05" stroke="#166534" stroke-width="0.8"/>
  <text x="632" y="124" fill="#6ee7b7" font-size="8.5" text-anchor="middle">Laser-drilled micro-via (25-50 µm dia)</text>
  <text x="522" y="135" fill="#6b7280" font-size="8">SAP = semi-additive process → enables L/S down to 2/2 µm</text>

  <!-- Spec table rows -->
  <text x="522" y="150" fill="#94a3b8" font-size="9" font-weight="600">Key specifications:</text>

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  <rect x="631" y="154" width="111" height="14" rx="2" fill="#111827" stroke="#374151" stroke-width="0.6"/>
  <text x="575" y="164" fill="#6b7280" font-size="8" text-anchor="middle">Parameter</text>
  <text x="686" y="164" fill="#6b7280" font-size="8" text-anchor="middle">Value</text>

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  <rect x="631" y="168" width="111" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <text x="575" y="178" fill="#e5e7eb" font-size="8" text-anchor="middle">Layer count</text>
  <text x="686" y="178" fill="#fcd34d" font-size="8" text-anchor="middle">4-20 signal layers</text>

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  <rect x="631" y="182" width="111" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <text x="575" y="192" fill="#e5e7eb" font-size="8" text-anchor="middle">Min L/S (adv.)</text>
  <text x="686" y="192" fill="#fcd34d" font-size="8" text-anchor="middle">2 µm / 2 µm</text>

  <rect x="522" y="196" width="107" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <rect x="631" y="196" width="111" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <text x="575" y="206" fill="#e5e7eb" font-size="8" text-anchor="middle">Dielectric Er</text>
  <text x="686" y="206" fill="#fcd34d" font-size="8" text-anchor="middle">3.0-3.5 (ABF-GX)</text>

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  <rect x="631" y="210" width="111" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <text x="575" y="220" fill="#e5e7eb" font-size="8" text-anchor="middle">Via diameter</text>
  <text x="686" y="220" fill="#fcd34d" font-size="8" text-anchor="middle">25-75 µm (laser)</text>

  <rect x="522" y="224" width="107" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <rect x="631" y="224" width="111" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <text x="575" y="234" fill="#e5e7eb" font-size="8" text-anchor="middle">Warpage control</text>
  <text x="686" y="234" fill="#fcd34d" font-size="8" text-anchor="middle">&lt;100 µm (HVM)</text>

  <rect x="522" y="238" width="107" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <rect x="631" y="238" width="111" height="14" rx="2" fill="#0e1320" stroke="#1f2937" stroke-width="0.5"/>
  <text x="575" y="248" fill="#e5e7eb" font-size="8" text-anchor="middle">Insertion loss</text>
  <text x="686" y="248" fill="#fcd34d" font-size="8" text-anchor="middle">0.5-1.5 dB/cm @28GHz</text>

  <!-- ── 3 Cards ── -->
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  <text x="126" y="276" fill="#fcd34d" font-size="9.5" font-weight="700" text-anchor="middle">Warpage — the #1 yield risk</text>
  <text x="18" y="289" fill="#e5e7eb" font-size="8.5">CTE mismatch: die Si (2.5 ppm/C) vs ABF (50-60 ppm/C)</text>
  <text x="18" y="301" fill="#e5e7eb" font-size="8.5">Large die + thin substrate = severe warpage during reflow</text>
  <text x="18" y="313" fill="#e5e7eb" font-size="8.5">Mitigations: stiffer core, stress-balanced build-up, underfill</text>
  <text x="18" y="325" fill="#e5e7eb" font-size="8.5">Panel warpage spec: &lt;3 mm (strip) before SMT assembly</text>
  <text x="18" y="337" fill="#6ee7b7" font-size="8.5">TSMC CoWoS: Si interposer eliminates CTE mismatch at die level</text>
  <text x="18" y="349" fill="#6b7280" font-size="8">ASE/Amkor/SPIL perform substrate assembly + test</text>

  <rect x="252" y="262" width="252" height="100" rx="6" fill="#0e1320" stroke="#334155" stroke-width="1"/>
  <text x="378" y="276" fill="#93c5fd" font-size="9.5" font-weight="700" text-anchor="middle">Signal Integrity in Substrate</text>
  <text x="262" y="289" fill="#e5e7eb" font-size="8.5">Impedance control: 50 Ohm single-ended, 100 Ohm differential</text>
  <text x="262" y="301" fill="#e5e7eb" font-size="8.5">Insertion loss rises sharply above 28 GHz — limits SerDes reach</text>
  <text x="262" y="313" fill="#e5e7eb" font-size="8.5">ETS (embedded trace substrate) buries traces for lower roughness</text>
  <text x="262" y="325" fill="#e5e7eb" font-size="8.5">Power planes + decap arrays manage PDN impedance &lt;1 MHz-5 GHz</text>
  <text x="262" y="337" fill="#fcd34d" font-size="8.5">Bump density limit sets max die-substrate bandwidth (I/O count)</text>
  <text x="262" y="349" fill="#6b7280" font-size="8">HBM uses 1024-bit bus on Si interposer — impossible on organic</text>

  <rect x="512" y="262" width="240" height="100" rx="6" fill="#0e1320" stroke="#334155" stroke-width="1"/>
  <text x="632" y="276" fill="#6ee7b7" font-size="9.5" font-weight="700" text-anchor="middle">Supply Chain</text>
  <text x="522" y="289" fill="#e5e7eb" font-size="8.5">Substrate makers: Ibiden, Shinko, Unimicron, AT&amp;S, Samsung EM</text>
  <text x="522" y="301" fill="#e5e7eb" font-size="8.5">ABF dielectric: Ajinomoto (near-monopoly on high-end ABF film)</text>
  <text x="522" y="313" fill="#e5e7eb" font-size="8.5">OSATs assemble die-on-substrate: ASE, Amkor, JCET, PTI</text>
  <text x="522" y="325" fill="#e5e7eb" font-size="8.5">Substrate often the lead-time bottleneck for HPC SoC launches</text>
  <text x="522" y="337" fill="#fcd34d" font-size="8.5">ABF shortage (2020-2022) constrained GPU + server CPU supply</text>
  <text x="522" y="349" fill="#6b7280" font-size="8">Substrate capacity build-out: $5B+ capex committed 2022-2026</text>

  <!-- ── Bottom stat bar ── -->
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  <text x="28" y="384" fill="#60a5fa" font-size="9" font-weight="600">4-20 layers</text>
  <text x="28" y="394" fill="#6b7280" font-size="8">signal + power planes</text>
  <line x1="115" y1="370" x2="115" y2="394" stroke="#1e3a5f" stroke-width="0.7"/>
  <text x="130" y="384" fill="#fcd34d" font-size="9" font-weight="600">2/2 µm L/S</text>
  <text x="130" y="394" fill="#6b7280" font-size="8">advanced SAP node</text>
  <line x1="215" y1="370" x2="215" y2="394" stroke="#1e3a5f" stroke-width="0.7"/>
  <text x="230" y="384" fill="#fbbf24" font-size="9" font-weight="600">150 µm → 1000 µm</text>
  <text x="230" y="394" fill="#6b7280" font-size="8">C4 bump to BGA pitch</text>
  <line x1="365" y1="370" x2="365" y2="394" stroke="#1e3a5f" stroke-width="0.7"/>
  <text x="380" y="384" fill="#f87171" font-size="9" font-weight="600">CTE 2.5 vs 50 ppm/C</text>
  <text x="380" y="394" fill="#6b7280" font-size="8">Si-to-organic warpage driver</text>
  <line x1="510" y1="370" x2="510" y2="394" stroke="#1e3a5f" stroke-width="0.7"/>
  <text x="525" y="384" fill="#6ee7b7" font-size="9" font-weight="600">Er = 3.0-3.5</text>
  <text x="525" y="394" fill="#6b7280" font-size="8">ABF dielectric constant</text>
  <line x1="620" y1="370" x2="620" y2="394" stroke="#1e3a5f" stroke-width="0.7"/>
  <text x="635" y="384" fill="#c4b5fd" font-size="9" font-weight="600">50%+ package cost</text>
  <text x="635" y="394" fill="#6b7280" font-size="8">substrate in advanced PKG</text>

  <text x="380" y="420" fill="#4b5563" font-size="8" text-anchor="middle">The substrate is the fan-out layer that makes fine die I/O accessible to board-level assembly — pitch transformation of 10-100x across 0.1-0.8 mm of organic dielectric</text>
  <text x="380" y="432" fill="#4b5563" font-size="8" text-anchor="middle">Intel, TSMC, Samsung, and AMD all depend on Ibiden and Shinko for advanced ABF substrates; supply constraints directly set chip product cadence</text>
</svg>

The substrate fan-out problem comes from the mismatch between die bump pitch and PCB trace pitch. Modern flip-chip dies have C4 bump pitches of 100-150 micrometers, while PCB traces are 80-150 micrometers wide but BGA solder balls are placed on 0.8-1.0 millimeter grids. The substrate must transition across this 6-10x pitch difference through 4-20 layers of copper traces and laser-drilled microvias, each layer patterned by semi-additive process (SAP) on Ajinomoto Build-up Film (ABF) dielectric.

ABF is the critical material. Ajinomoto's build-up film is a thermoset epoxy resin laminated as thin sheets onto the substrate core. After lamination, microvias are drilled by CO2 laser (25-75 micrometer diameter), then copper is deposited by electroless seeding followed by electrolytic plating. The SAP process enables line/space down to 2/2 micrometers in leading-edge substrates, compared to 10/10 micrometers in conventional subtractive etch. ABF's dielectric constant (Er 3.0-3.5) and loss tangent set the signal integrity ceiling for high-speed traces.

Warpage is the primary yield and reliability risk. Silicon has a CTE of 2.5 ppm/C while ABF organic laminate is around 50-60 ppm/C. A large die bonded to a thin substrate undergoes severe warpage during reflow soldering (around 260C for SAC305 solder) and during the subsequent temperature cycling qualification. Warpage exceeding 100-200 micrometers causes bump non-contact, underfill voids, and solder joint cracking. Mitigations include stiffer glass-fiber cores, stress-balanced copper patterns, molding compound stiffeners, and underfill encapsulant after flip-chip attach.

Advanced packaging replaces or supplements the organic substrate. Intel's EMIB embeds a small silicon bridge die inside the organic substrate to provide high-density routing (55 micrometer bump pitch) between chiplets without a full silicon interposer. TSMC's CoWoS places all chiplets on a large silicon interposer with RDL pitch below 10 micrometers — achieving the bandwidth density needed for HBM alongside a compute die. TSMC's SoIC and Samsung's X-Cube use direct copper-to-copper hybrid bonding with sub-micrometer pitch, eliminating the die-attach material entirely. The organic substrate remains as the package-level board interface beneath all these architectures.

Signal integrity in the substrate is governed by trace impedance control (50 ohm single-ended, 100 ohm differential), insertion loss (0.5-1.5 dB/cm at 28 GHz in ABF), and power delivery network impedance across 1 MHz to 5 GHz. Embedded trace substrates (ETS) bury the signal layer below the surface to reduce trace surface roughness and crosstalk. For HBM interfaces, the 1024-bit bus requires a silicon interposer — the organic substrate cannot achieve the required pitch density.

Supply chain concentration is a systemic risk. Ibiden and Shinko Electric dominate advanced ABF substrate production. Ajinomoto holds a near-monopoly on high-end ABF dielectric film. The 2020-2022 ABF shortage constrained GPU and server CPU supply across the industry, prompting over five billion dollars in announced substrate capacity expansions. Lead times for advanced substrate design qualification run 12-18 months, making substrate availability a gating factor in chip product launches.