<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Parasitic extraction: the wires themselves slow the chip down</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Turn the routed metal into R and C so timing sees the real, loaded delay of every net</text><!-- Panel 1: where parasitics come from --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Where they come from</text><text x="32" y="106" fill="#8b949e" font-size="10.5">a wire is not an ideal connection</text><rect x="42" y="118" width="182" height="150" rx="3" fill="#111a24" stroke="#30363d"/><!-- driver --><rect x="52" y="176" width="26" height="26" rx="2" fill="#38506a"/><text x="65" y="193" fill="#cfe4f5" font-size="8" text-anchor="middle">drv</text><!-- wire as R segments --><line x1="78" y1="189" x2="96" y2="189" stroke="#b8732e" stroke-width="3"/><rect x="96" y="184" width="18" height="10" fill="#e0913a"/><line x1="114" y1="189" x2="132" y2="189" stroke="#b8732e" stroke-width="3"/><rect x="132" y="184" width="18" height="10" fill="#e0913a"/><line x1="150" y1="189" x2="168" y2="189" stroke="#b8732e" stroke-width="3"/><!-- receiver --><rect x="168" y="176" width="26" height="26" rx="2" fill="#38506a"/><text x="181" y="193" fill="#cfe4f5" font-size="8" text-anchor="middle">rcv</text><text x="105" y="178" fill="#e0913a" font-size="8">R (metal)</text><!-- caps to ground --><line x1="105" y1="194" x2="105" y2="214" stroke="#38bdf8" stroke-width="1.5"/><line x1="99" y1="214" x2="111" y2="214" stroke="#38bdf8" stroke-width="2"/><line x1="141" y1="194" x2="141" y2="214" stroke="#38bdf8" stroke-width="1.5"/><line x1="135" y1="214" x2="147" y2="214" stroke="#38bdf8" stroke-width="2"/><text x="150" y="228" fill="#38bdf8" font-size="8">C to ground</text><!-- coupling cap between neighbors --><line x1="123" y1="240" x2="123" y2="252" stroke="#a99cf0" stroke-width="1.5"/><line x1="60" y1="246" x2="188" y2="246" stroke="#6b5fb0" stroke-width="1" stroke-dasharray="3,2"/><text x="52" y="262" fill="#a99cf0" font-size="8">Cc coupling to the neighbor net</text><text x="32" y="290" fill="#adb5bd" font-size="9.5">Every metal segment has series</text><text x="32" y="305" fill="#adb5bd" font-size="9.5">resistance, capacitance to ground, and</text><text x="32" y="320" fill="#adb5bd" font-size="9.5">coupling capacitance to its neighbors.</text><text x="32" y="335" fill="#adb5bd" font-size="9.5">Longer, narrower, denser wires carry</text><text x="32" y="350" fill="#adb5bd" font-size="9.5">more R and C &#8212; and more delay.</text><!-- Panel 2: the RC network / delay --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; RC delay on the net</text><text x="279" y="106" fill="#8b949e" font-size="10.5">R and C make the edge arrive late</text><rect x="287" y="118" width="196" height="120" rx="3" fill="#111a24" stroke="#30363d"/><!-- ideal step --><polyline points="300,214 330,214 330,140 470,140" fill="none" stroke="#8b949e" stroke-width="1.5" stroke-dasharray="4,3"/><text x="380" y="134" fill="#8b949e" font-size="8">ideal step</text><!-- rc curve --><path d="M300,214 L330,214 C360,214 350,150 470,144" fill="none" stroke="#38bdf8" stroke-width="2"/><text x="392" y="168" fill="#38bdf8" font-size="8">loaded (RC)</text><!-- delay marker --><line x1="330" y1="214" x2="330" y2="226" stroke="#f87171" stroke-width="1"/><line x1="372" y1="214" x2="372" y2="226" stroke="#f87171" stroke-width="1"/><line x1="330" y1="222" x2="372" y2="222" stroke="#f87171" stroke-width="1.5"/><text x="336" y="234" fill="#f87171" font-size="8">delay</text><text x="299" y="256" fill="#adb5bd" font-size="8.5">delay grows with R&#215;C (&#8776; wire length&#178;)</text><text x="279" y="284" fill="#adb5bd" font-size="9.5">The tool models each net as an RC tree</text><text x="279" y="299" fill="#adb5bd" font-size="9.5">and writes it to a SPEF file. Timing then</text><text x="279" y="314" fill="#adb5bd" font-size="9.5">re-analyzes paths with real wire loads &#8212;</text><text x="279" y="329" fill="#adb5bd" font-size="9.5">post-route slack, not the optimistic</text><text x="279" y="344" fill="#adb5bd" font-size="9.5">pre-route estimate.</text><!-- Panel 3: what it feeds --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; What extraction feeds</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the numbers signoff runs on</text><circle cx="532" cy="126" r="2.4" fill="#38bdf8"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">SPEF &#8594; timing</text><text x="542" y="143" fill="#8b949e" font-size="9">static timing uses real RC to sign off</text><text x="542" y="156" fill="#8b949e" font-size="9">setup and hold at every corner.</text><circle cx="532" cy="176" r="2.4" fill="#a99cf0"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Crosstalk &amp; noise</text><text x="542" y="193" fill="#8b949e" font-size="9">coupling caps let tools model a neighbor</text><text x="542" y="206" fill="#8b949e" font-size="9">switching and glitching a quiet net.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Power &amp; IR / EM</text><text x="542" y="243" fill="#8b949e" font-size="9">wire R sets IR-drop and electromigration</text><text x="542" y="256" fill="#8b949e" font-size="9">limits on the power grid.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#f87171" font-size="10" font-weight="700">Accuracy vs runtime</text><text x="536" y="306" fill="#adb5bd" font-size="9">Full 3D field solve is most accurate but</text><text x="536" y="320" fill="#adb5bd" font-size="9">slow; rule-based extraction is fast and</text><text x="536" y="334" fill="#adb5bd" font-size="9">good enough for most nets. Tools mix</text><text x="536" y="348" fill="#adb5bd" font-size="9">both &#8212; solver only where it matters.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#e0913a" font-size="11" font-weight="700">Resistance</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Series R of the metal &#8212; longer and</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">narrower wires resist more.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#38bdf8" font-size="11" font-weight="700">Capacitance</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">To ground and to neighbors &#8212; sets</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">how much charge each edge must move.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#c4b5fd" font-size="11" font-weight="700">SPEF &#8594; signoff</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">The extracted RC that makes timing,</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">noise and power analysis real.</text></svg>

Parasitic Extraction is the computational process of determining the unintended capacitance, resistance, and inductance arising from the physical layout of interconnect wires, vias, and substrate — annotating the circuit netlist with these parasitics so that post-layout simulation accurately predicts real-chip timing, power, and signal integrity — the critical signoff step without which no advanced semiconductor chip can be taped out with confidence that it will function at the target frequency.

What Is Parasitic Extraction?

• Definition: Analyzing the 3D geometry of metal routing, vias, dielectric layers, and substrate to compute the electrical parasitics (R, C, L) that affect signal propagation but are not represented in the schematic-level netlist.
• Extraction Types: R-only (wire resistance from geometry and sheet resistance), C-only (coupling and ground capacitance from 3D field solutions), RC (combined for timing analysis — the dominant signoff mode), and RLC (including inductance for high-frequency or high-speed I/O circuits).
• Output Format: SPEF (Standard Parasitic Exchange Format) or DSPF (Detailed Standard Parasitic Format) files that annotate the logical netlist with physical parasitics for simulation.
• Accuracy Requirement: Sub-femtofarad capacitance accuracy and sub-milliohm resistance accuracy at advanced nodes where parasitics dominate over gate delays.

Why Parasitic Extraction Matters

• Timing Dominance: At 7 nm and below, interconnect RC delay accounts for 60–80% of total path delay — accurate extraction is essential for timing closure.
• Power Accuracy: Dynamic power (CV²f) depends directly on extracted capacitance — extraction errors of 5% translate to 5% power estimation error.
• Signal Integrity: Coupling capacitance between adjacent wires causes crosstalk — extraction must capture these coupling parasitics for noise analysis.
• IR Drop: Extracted resistance of power delivery network determines voltage droop across the chip — critical for functional and timing analysis.
• Signoff Confidence: Chips taped out with inaccurate parasitics may fail at target frequency, costing $5M+ per mask respins at advanced nodes.

Extraction Methodology

Field Solver Approach:

• Solve Maxwell's equations (or Laplace's equation for capacitance) on the 3D interconnect geometry.
• Most accurate but computationally expensive — used for critical nets and technology characterization.
• Tools: Synopsys RCX, Cadence Quantus QRC in field-solver mode.

Pattern Matching Approach:

• Pre-characterize parasitic values for canonical geometric patterns (parallel wires, crossing wires, vias, bends).
• During extraction, match actual layout geometries to pre-computed patterns and interpolate.
• 100× faster than field solving with 1–3% accuracy loss — the production extraction mode.

Extraction Accuracy Tiers

Extraction Challenges at Advanced Nodes

• Multi-Patterning Effects: SADP/SAQP introduce systematic width and spacing variations that extraction must capture.
• Barrier and Liner Impact: At sub-20 nm wire widths, barrier metal (TaN/Ta) occupies >30% of wire cross-section — extraction must model the resistivity difference.
• BEOL Scaling: Copper resistivity increases dramatically below 30 nm width due to electron scattering — extraction needs resistivity models beyond bulk copper.
• 3D Integration: TSVs and hybrid bonding introduce vertical parasitics spanning multiple die — extraction must handle chiplet boundaries.

Parasitic Extraction is the bridge between physical design and electrical reality — transforming geometric layout data into the electrical model that determines whether a chip will meet its timing, power, and signal integrity targets, making it an indispensable signoff requirement for every advanced semiconductor design.