<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Parasitic extraction: the wires themselves slow the chip down</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Turn the routed metal into R and C so timing sees the real, loaded delay of every net</text><!-- Panel 1: where parasitics come from --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Where they come from</text><text x="32" y="106" fill="#8b949e" font-size="10.5">a wire is not an ideal connection</text><rect x="42" y="118" width="182" height="150" rx="3" fill="#111a24" stroke="#30363d"/><!-- driver --><rect x="52" y="176" width="26" height="26" rx="2" fill="#38506a"/><text x="65" y="193" fill="#cfe4f5" font-size="8" text-anchor="middle">drv</text><!-- wire as R segments --><line x1="78" y1="189" x2="96" y2="189" stroke="#b8732e" stroke-width="3"/><rect x="96" y="184" width="18" height="10" fill="#e0913a"/><line x1="114" y1="189" x2="132" y2="189" stroke="#b8732e" stroke-width="3"/><rect x="132" y="184" width="18" height="10" fill="#e0913a"/><line x1="150" y1="189" x2="168" y2="189" stroke="#b8732e" stroke-width="3"/><!-- receiver --><rect x="168" y="176" width="26" height="26" rx="2" fill="#38506a"/><text x="181" y="193" fill="#cfe4f5" font-size="8" text-anchor="middle">rcv</text><text x="105" y="178" fill="#e0913a" font-size="8">R (metal)</text><!-- caps to ground --><line x1="105" y1="194" x2="105" y2="214" stroke="#38bdf8" stroke-width="1.5"/><line x1="99" y1="214" x2="111" y2="214" stroke="#38bdf8" stroke-width="2"/><line x1="141" y1="194" x2="141" y2="214" stroke="#38bdf8" stroke-width="1.5"/><line x1="135" y1="214" x2="147" y2="214" stroke="#38bdf8" stroke-width="2"/><text x="150" y="228" fill="#38bdf8" font-size="8">C to ground</text><!-- coupling cap between neighbors --><line x1="123" y1="240" x2="123" y2="252" stroke="#a99cf0" stroke-width="1.5"/><line x1="60" y1="246" x2="188" y2="246" stroke="#6b5fb0" stroke-width="1" stroke-dasharray="3,2"/><text x="52" y="262" fill="#a99cf0" font-size="8">Cc coupling to the neighbor net</text><text x="32" y="290" fill="#adb5bd" font-size="9.5">Every metal segment has series</text><text x="32" y="305" fill="#adb5bd" font-size="9.5">resistance, capacitance to ground, and</text><text x="32" y="320" fill="#adb5bd" font-size="9.5">coupling capacitance to its neighbors.</text><text x="32" y="335" fill="#adb5bd" font-size="9.5">Longer, narrower, denser wires carry</text><text x="32" y="350" fill="#adb5bd" font-size="9.5">more R and C &#8212; and more delay.</text><!-- Panel 2: the RC network / delay --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; RC delay on the net</text><text x="279" y="106" fill="#8b949e" font-size="10.5">R and C make the edge arrive late</text><rect x="287" y="118" width="196" height="120" rx="3" fill="#111a24" stroke="#30363d"/><!-- ideal step --><polyline points="300,214 330,214 330,140 470,140" fill="none" stroke="#8b949e" stroke-width="1.5" stroke-dasharray="4,3"/><text x="380" y="134" fill="#8b949e" font-size="8">ideal step</text><!-- rc curve --><path d="M300,214 L330,214 C360,214 350,150 470,144" fill="none" stroke="#38bdf8" stroke-width="2"/><text x="392" y="168" fill="#38bdf8" font-size="8">loaded (RC)</text><!-- delay marker --><line x1="330" y1="214" x2="330" y2="226" stroke="#f87171" stroke-width="1"/><line x1="372" y1="214" x2="372" y2="226" stroke="#f87171" stroke-width="1"/><line x1="330" y1="222" x2="372" y2="222" stroke="#f87171" stroke-width="1.5"/><text x="336" y="234" fill="#f87171" font-size="8">delay</text><text x="299" y="256" fill="#adb5bd" font-size="8.5">delay grows with R&#215;C (&#8776; wire length&#178;)</text><text x="279" y="284" fill="#adb5bd" font-size="9.5">The tool models each net as an RC tree</text><text x="279" y="299" fill="#adb5bd" font-size="9.5">and writes it to a SPEF file. Timing then</text><text x="279" y="314" fill="#adb5bd" font-size="9.5">re-analyzes paths with real wire loads &#8212;</text><text x="279" y="329" fill="#adb5bd" font-size="9.5">post-route slack, not the optimistic</text><text x="279" y="344" fill="#adb5bd" font-size="9.5">pre-route estimate.</text><!-- Panel 3: what it feeds --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; What extraction feeds</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the numbers signoff runs on</text><circle cx="532" cy="126" r="2.4" fill="#38bdf8"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">SPEF &#8594; timing</text><text x="542" y="143" fill="#8b949e" font-size="9">static timing uses real RC to sign off</text><text x="542" y="156" fill="#8b949e" font-size="9">setup and hold at every corner.</text><circle cx="532" cy="176" r="2.4" fill="#a99cf0"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Crosstalk &amp; noise</text><text x="542" y="193" fill="#8b949e" font-size="9">coupling caps let tools model a neighbor</text><text x="542" y="206" fill="#8b949e" font-size="9">switching and glitching a quiet net.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Power &amp; IR / EM</text><text x="542" y="243" fill="#8b949e" font-size="9">wire R sets IR-drop and electromigration</text><text x="542" y="256" fill="#8b949e" font-size="9">limits on the power grid.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#f87171" font-size="10" font-weight="700">Accuracy vs runtime</text><text x="536" y="306" fill="#adb5bd" font-size="9">Full 3D field solve is most accurate but</text><text x="536" y="320" fill="#adb5bd" font-size="9">slow; rule-based extraction is fast and</text><text x="536" y="334" fill="#adb5bd" font-size="9">good enough for most nets. Tools mix</text><text x="536" y="348" fill="#adb5bd" font-size="9">both &#8212; solver only where it matters.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#e0913a" font-size="11" font-weight="700">Resistance</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Series R of the metal &#8212; longer and</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">narrower wires resist more.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#38bdf8" font-size="11" font-weight="700">Capacitance</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">To ground and to neighbors &#8212; sets</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">how much charge each edge must move.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#c4b5fd" font-size="11" font-weight="700">SPEF &#8594; signoff</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">The extracted RC that makes timing,</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">noise and power analysis real.</text></svg>

Parasitic Extraction is the post-layout analysis process that computes the resistance (R), capacitance (C), and inductance (L) of every metal wire, via, and device interconnection in the physical layout — converting the geometric shapes of the routed design into an electrical RC/RCL netlist that accurately models signal delay, power consumption, crosstalk, and IR-drop for timing sign-off, power analysis, and signal integrity verification.

Why Parasitic Extraction Is Essential

At advanced nodes, interconnect delay exceeds transistor switching delay. A 1mm wire on M3 at the 5nm node has ~50 Ohm resistance and ~50 fF capacitance, contributing ~2.5 ps of RC delay per mm — comparable to a gate delay. Without accurate parasitic modeling, timing analysis would be wildly optimistic, and chips would fail at speed.

What Gets Extracted

• Wire Resistance: Depends on metal resistivity, wire width, length, and thickness. At sub-20nm widths, surface and grain-boundary scattering increase effective resistivity by 2-5x above bulk copper.
• Grounded Capacitance (Cg): Capacitance between a wire and the reference planes (VSS, VDD) above and below. Depends on wire geometry and ILD thickness/permittivity.
• Coupling Capacitance (Cc): Capacitance between adjacent wires on the same or neighboring metal layers. Dominates at tight pitches — Cc is 50-70% of total capacitance at sub-28nm metal pitches.
• Via Resistance: Each via has contact resistance (0.5-5 Ohm/via at advanced nodes). Via arrays in the power grid contribute significantly to IR-drop.
• Inductance: Important only for wide global buses and clock networks where inductive effects (Ldi/dt) cause supply noise. Typically extracted only for selected nets.

Extraction Methods

• Rule-Based: Pre-computed lookup tables map geometric configurations (wire width, spacing, layer stack) to parasitic values. Fastest method (~1-2 hours for full chip) but limited accuracy for complex 3D geometries.
• Field-Solver Based: Solves Maxwell's equations (or Laplace's equation in the quasi-static approximation) for the actual 3D geometry of each extracted region. Most accurate (1-2% error vs. measured silicon) but 5-10x slower than rule-based.
• Hybrid: Rule-based for most of the chip, field-solver for critical nets. The production standard for sign-off extraction.

Extraction Accuracy vs. Silicon

Extraction tools are calibrated against silicon measurements (ring oscillator delays, interconnect test structures). The acceptable correlation error for sign-off is <3-5% for delay and <5-10% for capacitance across all metal layers and geometries.

Parasitic Extraction is the translation layer between geometry and electricity — converting the physical shapes drawn by the place-and-route tool into the electrical models that determine whether the chip meets its performance, power, and signal integrity specifications.