is the high-speed serial interconnect…

Home› Knowledge Base› is the high-speed serial interconnect that attaches almost every performance device inside a computer — GPUs, NVMe SSDs, network cards, and accelerators — to the CPU. It replaced the old shared parallel PCI bus with a switched fabric of independent point-to-point links, and it has become the backbone standard that other interconnects build on: NVMe runs over it, and CXL literally reuses its physical layer. For AI systems, PCIe is the road that feeds data to and from GPUs, and its bandwidth is often the thing standing between the accelerators and the rest of the machine.\n\n```svg\n\n \n PCIe — Peripheral Component Interconnect Express\n the serial, point-to-point link that connects CPUs to GPUs, SSDs, and NICs\n Point-to-point tree topology\n \n CPU / Root Complex\n owns the PCIe domain\n \n PCIe switch\n \n \n GPU\n \n link\n \n NVMe SSD\n \n link\n \n NIC\n \n link\n every link is a private point-to-point connection, not a shared bus\n \n A link = 1 to 16 lanes (x1 … x16)\n each lane = 2 differential pairs (one per direction),\n serial and full-duplex — add lanes to add bandwidth\n Bandwidth doubles almost every generation\n \n Gen1\n 2.5GT/s\n \n Gen2\n 5GT/s\n \n Gen3\n 8GT/s\n \n Gen4\n 16GT/s\n \n Gen5\n 32GT/s\n \n Gen6\n 64GT/s\n per-lane rate; a x16 Gen5 link ≈ 64 GB/s each way\n Gen6 switches to PAM4 signaling to keep doubling\n\n```\n\n
<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
  <rect x="0" y="0" width="760" height="470" fill="#0d1117"/>
  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">PCIe — The Universal High-Speed Interconnect</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">serial lanes, packet-based protocol — connects GPU, NVMe, NIC, and CXL to the CPU</text>

  <!-- === TOP: Physical link (lanes) === -->
  <rect x="30" y="62" width="700" height="100" rx="6" fill="#080d14" stroke="#233043" stroke-width="1.2"/>
  <text x="380" y="80" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">Physical Link — Differential SerDes Lanes</text>

  <!-- Root Complex (CPU) -->
  <rect x="50" y="95" width="100" height="45" rx="4" fill="#122040" stroke="#60a5fa" stroke-width="1.2"/>
  <text x="100" y="115" fill="#93c5fd" font-size="9" text-anchor="middle" font-weight="600">Root Complex</text>
  <text x="100" y="130" fill="#6b7684" font-size="8" text-anchor="middle">(CPU/chipset)</text>

  <!-- Lanes (differential pairs) -->
  <g stroke="#34d399" stroke-width="1">
    <line x1="150" y1="105" x2="490" y2="105"/>
    <line x1="150" y1="112" x2="490" y2="112"/>
  </g>
  <g stroke="#34d399" stroke-width="0.7" opacity="0.5">
    <line x1="150" y1="119" x2="490" y2="119"/>
    <line x1="150" y1="124" x2="490" y2="124"/>
    <line x1="150" y1="131" x2="490" y2="131"/>
    <line x1="150" y1="136" x2="490" y2="136"/>
  </g>
  <text x="320" y="100" fill="#6ee7b7" font-size="8" text-anchor="middle">TX differential pair (lane 0)</text>
  <text x="320" y="148" fill="#6b7684" font-size="7.5" text-anchor="middle">x1, x4, x8, or x16 lanes</text>

  <!-- Endpoint (GPU/NVMe) -->
  <rect x="495" y="95" width="100" height="45" rx="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="1.2"/>
  <text x="545" y="115" fill="#fbbf24" font-size="9" text-anchor="middle" font-weight="600">Endpoint</text>
  <text x="545" y="130" fill="#6b7684" font-size="8" text-anchor="middle">(GPU / NVMe / NIC)</text>

  <!-- Bandwidth annotation -->
  <rect x="610" y="95" width="105" height="45" rx="3" fill="#14261f" stroke="#34d399" stroke-width="0.8"/>
  <text x="662" y="109" fill="#6ee7b7" font-size="8" text-anchor="middle">x16 bandwidth:</text>
  <text x="662" y="121" fill="#34d399" font-size="8.5" text-anchor="middle">Gen5: 64 GB/s</text>
  <text x="662" y="133" fill="#fbbf24" font-size="8.5" text-anchor="middle">Gen6: 128 GB/s</text>

  <!-- === MIDDLE LEFT: Protocol Stack === -->
  <rect x="30" y="175" width="260" height="160" rx="6" fill="#0b1220" stroke="#233043" stroke-width="1"/>
  <text x="160" y="193" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Protocol Stack (layered)</text>

  <!-- Transaction layer -->
  <rect x="50" y="205" width="220" height="28" rx="3" fill="#1a1520" stroke="#a78bfa" stroke-width="1"/>
  <text x="160" y="218" fill="#c4b5fd" font-size="9" text-anchor="middle">Transaction Layer (TLP)</text>
  <text x="160" y="228" fill="#8b98a5" font-size="7.5" text-anchor="middle">read/write/config/msg packets</text>

  <!-- Data link layer -->
  <rect x="50" y="238" width="220" height="28" rx="3" fill="#14261f" stroke="#34d399" stroke-width="1"/>
  <text x="160" y="251" fill="#6ee7b7" font-size="9" text-anchor="middle">Data Link Layer (DLLP)</text>
  <text x="160" y="261" fill="#8b98a5" font-size="7.5" text-anchor="middle">ACK/NAK, flow control, CRC</text>

  <!-- Physical layer -->
  <rect x="50" y="271" width="220" height="28" rx="3" fill="#0f1a2a" stroke="#60a5fa" stroke-width="1"/>
  <text x="160" y="284" fill="#93c5fd" font-size="9" text-anchor="middle">Physical Layer (PHY)</text>
  <text x="160" y="294" fill="#8b98a5" font-size="7.5" text-anchor="middle">SerDes, encoding, equalization</text>

  <!-- Encoding note -->
  <text x="160" y="318" fill="#6b7684" font-size="8" text-anchor="middle">Gen3-5: 128b/130b | Gen6: PAM4 + 1b/1b (FLIT)</text>
  <text x="160" y="332" fill="#6b7684" font-size="7.5" text-anchor="middle">Gen6: fixed 256B FLIT (no framing overhead)</text>

  <!-- === MIDDLE RIGHT: Gen evolution === -->
  <rect x="310" y="175" width="420" height="160" rx="6" fill="#0b1220" stroke="#233043" stroke-width="1"/>
  <text x="520" y="193" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">PCIe Generation Evolution</text>

  <!-- Table-like layout -->
  <text x="340" y="215" fill="#6b7684" font-size="8.5">Gen3 (2010):</text>
  <text x="440" y="215" fill="#8b98a5" font-size="8.5">8 GT/s NRZ</text>
  <text x="560" y="215" fill="#8b98a5" font-size="8.5">~1 GB/s/lane</text>
  <text x="660" y="215" fill="#6b7684" font-size="8">mainstream</text>

  <text x="340" y="233" fill="#6b7684" font-size="8.5">Gen4 (2017):</text>
  <text x="440" y="233" fill="#8b98a5" font-size="8.5">16 GT/s NRZ</text>
  <text x="560" y="233" fill="#8b98a5" font-size="8.5">~2 GB/s/lane</text>
  <text x="660" y="233" fill="#6b7684" font-size="8">NVMe SSD</text>

  <text x="340" y="251" fill="#60a5fa" font-size="8.5">Gen5 (2019):</text>
  <text x="440" y="251" fill="#60a5fa" font-size="8.5">32 GT/s NRZ</text>
  <text x="560" y="251" fill="#60a5fa" font-size="8.5">~4 GB/s/lane</text>
  <text x="660" y="251" fill="#60a5fa" font-size="8">GPU/CXL</text>

  <text x="340" y="269" fill="#fbbf24" font-size="8.5" font-weight="600">Gen6 (2025):</text>
  <text x="440" y="269" fill="#fbbf24" font-size="8.5">64 GT/s PAM4</text>
  <text x="560" y="269" fill="#fbbf24" font-size="8.5">~8 GB/s/lane</text>
  <text x="660" y="269" fill="#fbbf24" font-size="8">AI/CXL 3.0</text>

  <text x="340" y="287" fill="#f87171" font-size="8.5">Gen7 (~2028):</text>
  <text x="440" y="287" fill="#f87171" font-size="8.5">128 GT/s PAM4</text>
  <text x="560" y="287" fill="#f87171" font-size="8.5">~16 GB/s/lane</text>

  <text x="520" y="310" fill="#8b98a5" font-size="8" text-anchor="middle">each gen: 2x bandwidth, same connector form factor</text>
  <text x="520" y="325" fill="#6b7684" font-size="7.5" text-anchor="middle">backward compatible: Gen5 card in Gen3 slot works (at Gen3 speed)</text>

  <!-- === BOTTOM: What uses PCIe === -->
  <rect x="30" y="348" width="700" height="72" rx="5" fill="#0b1220" stroke="#233043" stroke-width="1"/>
  <text x="380" y="366" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">What Plugs Into PCIe</text>

  <text x="90" y="388" fill="#76b900" font-size="9" text-anchor="middle" font-weight="600">GPU (x16)</text>
  <text x="90" y="402" fill="#6b7684" font-size="8" text-anchor="middle">64 GB/s (Gen5)</text>

  <text x="210" y="388" fill="#60a5fa" font-size="9" text-anchor="middle" font-weight="600">NVMe SSD (x4)</text>
  <text x="210" y="402" fill="#6b7684" font-size="8" text-anchor="middle">14 GB/s read</text>

  <text x="340" y="388" fill="#c4b5fd" font-size="9" text-anchor="middle" font-weight="600">CXL (x16)</text>
  <text x="340" y="402" fill="#6b7684" font-size="8" text-anchor="middle">coherent memory</text>

  <text x="460" y="388" fill="#fbbf24" font-size="9" text-anchor="middle" font-weight="600">NIC (x16)</text>
  <text x="460" y="402" fill="#6b7684" font-size="8" text-anchor="middle">400G RDMA</text>

  <text x="570" y="388" fill="#34d399" font-size="9" text-anchor="middle" font-weight="600">FPGA (x16)</text>
  <text x="570" y="402" fill="#6b7684" font-size="8" text-anchor="middle">accel/SmartNIC</text>

  <text x="670" y="388" fill="#8b98a5" font-size="9" text-anchor="middle" font-weight="600">USB4/TB</text>
  <text x="670" y="402" fill="#6b7684" font-size="8" text-anchor="middle">tunneled</text>

  <!-- CXL note -->
  <text x="380" y="430" fill="#e6edf3" font-size="9.5" text-anchor="middle" font-weight="600">CXL (Compute Express Link): cache-coherent protocol OVER PCIe PHY — same wires, richer semantics</text>
  <text x="380" y="445" fill="#8b98a5" font-size="9" text-anchor="middle">CXL.mem enables pooled/shared memory across hosts — the future of disaggregated AI infrastructure</text>

  <text x="380" y="464" fill="#6b7684" font-size="11" text-anchor="middle">PCIe is the USB of chips — every accelerator, every SSD, every network card speaks it. 30 years and counting.</text>
</svg>
```Ie (PCI Express)** is the high-speed serial interconnect that attaches almost every performance device inside a computer — GPUs, NVMe SSDs, network cards, and accelerators — to the CPU. It replaced the old shared parallel PCI bus with a switched fabric of independent point-to-point links, and it has become the backbone standard that other interconnects build on: NVMe runs over it, and CXL literally reuses its physical layer. For AI systems, PCIe is the road that feeds data to and from GPUs, and its bandwidth is often the thing standing between the accelerators and the rest of the machine.\n\n```svg\n<svg viewBox="0 0 700 392" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">\n  <rect x="0" y="0" width="700" height="392" fill="#0d1117"/>\n  <text x="350" y="30" fill="#e6edf3" font-size="20" font-weight="700" text-anchor="middle">PCIe — Peripheral Component Interconnect Express</text>\n  <text x="350" y="52" fill="#8b98a5" font-size="12" text-anchor="middle">the serial, point-to-point link that connects CPUs to GPUs, SSDs, and NICs</text>\n  <text x="40" y="88" fill="#cbd5e1" font-size="12.5" font-weight="700">Point-to-point tree topology</text>\n  <rect x="120" y="100" width="140" height="38" rx="7" fill="#2a1420" stroke="#fbbf24" stroke-width="1.5"/>\n  <text x="190" y="118" fill="#fcd34d" font-size="13" font-weight="700" text-anchor="middle">CPU / Root Complex</text>\n  <text x="190" y="132" fill="#8b98a5" font-size="13" text-anchor="middle">owns the PCIe domain</text>\n  <rect x="130" y="168" width="120" height="34" rx="7" fill="#101826" stroke="#38bdf8" stroke-width="1.5"/>\n  <text x="190" y="190" fill="#7dd3fc" font-size="13" text-anchor="middle">PCIe switch</text>\n  <line x1="190" y1="138" x2="190" y2="168" stroke="#3f5169" stroke-width="1.6"/>\n  <rect x="40" y="240" width="86" height="38" rx="7" fill="#0b1220" stroke="#34d399" stroke-width="1.5"/>\n  <text x="83" y="263" fill="#34d399" font-size="12" text-anchor="middle">GPU</text>\n  <line x1="190" y1="202" x2="83" y2="240" stroke="#3f5169" stroke-width="1.4"/>\n  <text x="132" y="224" fill="#6b7684" font-size="12" text-anchor="middle">link</text>\n  <rect x="140" y="240" width="86" height="38" rx="7" fill="#0b1220" stroke="#c084fc" stroke-width="1.5"/>\n  <text x="183" y="263" fill="#c084fc" font-size="12" text-anchor="middle">NVMe SSD</text>\n  <line x1="190" y1="202" x2="183" y2="240" stroke="#3f5169" stroke-width="1.4"/>\n  <text x="182" y="224" fill="#6b7684" font-size="12" text-anchor="middle">link</text>\n  <rect x="240" y="240" width="86" height="38" rx="7" fill="#0b1220" stroke="#818cf8" stroke-width="1.5"/>\n  <text x="283" y="263" fill="#818cf8" font-size="12" text-anchor="middle">NIC</text>\n  <line x1="190" y1="202" x2="283" y2="240" stroke="#3f5169" stroke-width="1.4"/>\n  <text x="232" y="224" fill="#6b7684" font-size="12" text-anchor="middle">link</text>\n  <text x="185" y="300" fill="#6b7684" font-size="12" text-anchor="middle">every link is a private point-to-point connection, not a shared bus</text>\n  <rect x="40" y="320" width="300" height="54" rx="7" fill="#0b1220" stroke="#233043" stroke-width="1.5"/>\n  <text x="56" y="339" fill="#cbd5e1" font-size="12" font-weight="700">A link = 1 to 16 lanes (x1 … x16)</text>\n  <text x="56" y="356" fill="#8b98a5" font-size="12">each lane = 2 differential pairs (one per direction),</text>\n  <text x="56" y="368" fill="#8b98a5" font-size="12">serial and full-duplex — add lanes to add bandwidth</text>\n  <text x="380" y="88" fill="#cbd5e1" font-size="12.5" font-weight="700">Bandwidth doubles almost every generation</text>\n  <rect x="390" y="294" width="44" height="6" rx="3" fill="#60a5fa" opacity="0.85"/>\n  <text x="412.0" y="313" fill="#8b98a5" font-size="12" text-anchor="middle">Gen1</text>\n  <text x="412.0" y="289" fill="#c9d4e0" font-size="12" text-anchor="middle">2.5GT/s</text>\n  <rect x="440" y="288" width="44" height="12" rx="3" fill="#60a5fa" opacity="0.85"/>\n  <text x="462.0" y="313" fill="#8b98a5" font-size="12" text-anchor="middle">Gen2</text>\n  <text x="462.0" y="283" fill="#c9d4e0" font-size="12" text-anchor="middle">5GT/s</text>\n  <rect x="490" y="281" width="44" height="19" rx="3" fill="#60a5fa" opacity="0.85"/>\n  <text x="512.0" y="313" fill="#8b98a5" font-size="12" text-anchor="middle">Gen3</text>\n  <text x="512.0" y="276" fill="#c9d4e0" font-size="12" text-anchor="middle">8GT/s</text>\n  <rect x="540" y="262" width="44" height="38" rx="3" fill="#60a5fa" opacity="0.85"/>\n  <text x="562.0" y="313" fill="#8b98a5" font-size="12" text-anchor="middle">Gen4</text>\n  <text x="562.0" y="258" fill="#c9d4e0" font-size="12" text-anchor="middle">16GT/s</text>\n  <rect x="590" y="225" width="44" height="75" rx="3" fill="#34d399" opacity="0.85"/>\n  <text x="612.0" y="313" fill="#8b98a5" font-size="12" text-anchor="middle">Gen5</text>\n  <text x="612.0" y="220" fill="#c9d4e0" font-size="12" text-anchor="middle">32GT/s</text>\n  <rect x="640" y="150" width="44" height="150" rx="3" fill="#34d399" opacity="0.85"/>\n  <text x="662.0" y="313" fill="#8b98a5" font-size="12" text-anchor="middle">Gen6</text>\n  <text x="662.0" y="145" fill="#c9d4e0" font-size="12" text-anchor="middle">64GT/s</text>\n  <text x="390" y="330" fill="#6b7684" font-size="13">per-lane rate; a x16 Gen5 link ≈ 64 GB/s each way</text>\n  <text x="390" y="344" fill="#6b7684" font-size="13">Gen6 switches to PAM4 signaling to keep doubling</text>\n</svg>\n```\n\n**PCIe is point-to-point and switched, not a shared bus.** Each device gets its own dedicated link to the root complex (in the CPU) or to a PCIe switch, so devices do not contend for a common bus the way legacy PCI did. This gives every endpoint full, predictable bandwidth and lets the topology scale out as a tree of links and switches rather than a single bottleneck.\n\n**Bandwidth is built from lanes.** A single lane is a pair of differential wires in each direction — a full-duplex serial connection. Links are assembled from 1, 4, 8, or 16 lanes (written x1, x4, x8, x16), and bandwidth scales almost linearly with lane count, which is why GPUs take a x16 slot while a modest SSD is happy with x4. The serial, differential design is what lets each lane run at multi-gigahertz rates over a cheap connector.\n\n**Each generation roughly doubles the per-lane rate.** From Gen1's 2.5 GT/s to Gen3's 8, Gen4's 16, Gen5's 32, and Gen6's 64 GT/s, the transfer rate has doubled about every generation. A x16 Gen5 link delivers on the order of 64 GB/s in each direction. Gen6 changes the signaling from simple on/off (NRZ) to four-level PAM4 to keep doubling the rate without doubling the clock, borrowing a trick from high-end SerDes.\n\n**It is layered like a network protocol.** PCIe organizes communication into a transaction layer (the read/write/message requests software cares about), a data-link layer (sequence numbers, acknowledgments, and retries for reliability), and a physical layer (the SerDes, encoding, and electrical signaling on the wire). This layering is why PCIe can guarantee reliable, ordered delivery while still running at extreme serial speeds.\n\n**PCIe is the foundation other standards extend.** NVMe defines how SSDs talk over PCIe; CXL adds cache coherence and memory semantics on top of the same PCIe electricals; many accelerators and even some chip-to-chip links reuse PCIe PHYs. Understanding PCIe lanes, generations, and topology is therefore the entry point to understanding most of the interconnect stack around modern compute.\n\n| Generation | Per-lane rate | ~x16 each way | Signaling |\n|---|---|---|---|\n| Gen3 | 8 GT/s | ~16 GB/s | NRZ |\n| Gen4 | 16 GT/s | ~32 GB/s | NRZ |\n| Gen5 | 32 GT/s | ~64 GB/s | NRZ |\n| Gen6 | 64 GT/s | ~128 GB/s | PAM4 |\n\nRead PCIe through a *lanes-and-generations* lens rather than a *slot* lens: a device's real throughput is the product of how many lanes it negotiates and which generation both ends support, and a fast GPU in a link-starved slot (too few lanes or an older generation) is quietly bottlenecked. Because NVMe and CXL ride on the very same physical layer, the lane budget and generation of your PCIe fabric set the ceiling for storage, memory expansion, and accelerator feeding alike.\n
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