PLL (Phase-Locked Loop) — a feedback circuit that generates a stable, precise output clock locked in phase and frequency to a reference clock, essential for clock generation and data recovery in every digital chip.

Basic Architecture

<svg viewBox="0 0 603 93" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="603" height="93" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">Ref Clock </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> [Phase Detector] </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> [Loop Filter] </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> [VCO] </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> Output Clock</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">                </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9">                                    |</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#c9d1d9">                </tspan><tspan fill="#6e7681">└────────</tspan><tspan fill="#c9d1d9"> [Feedback Divider ÷N] </tspan><tspan fill="#6e7681">─────┘</tspan></text></g></svg>

• Phase/Frequency Detector (PFD): Compares reference and feedback phase
• Charge Pump: Converts PFD output to current pulses
• Loop Filter: Smooths current into control voltage (determines bandwidth/stability)
• VCO: Voltage-Controlled Oscillator — generates output frequency proportional to control voltage
• Divider: Divides output frequency by N for feedback (output = N × reference)

Key Specifications

• Lock range: Frequency range the PLL can track
• Jitter: Timing uncertainty on output clock edges (ps RMS). Critical for high-speed interfaces
• Lock time: How quickly PLL locks to reference after startup
• Phase noise: Spectral purity of output (dBc/Hz)

Applications on Chip

• Clock multiplication: 100MHz reference → 3GHz core clock
• Clock de-skewing: Align internal clock to external reference
• SerDes CDR (Clock Data Recovery): Extract clock from incoming data stream
• Frequency synthesis: Generate multiple frequencies from one crystal

Every digital chip contains at least one PLL — high-performance SoCs may have 10–20 PLLs for different clock domains.