PSG and BPSG Dielectrics is the use of phosphorus-doped (PSG) and boron-phosphorus-doped (BPSG) silicon dioxide — with viscous reflow at 850-950°C for gap-fill and planarization — providing a method for topography smoothing and interlayer dielectric integration in pre-high-k CMOS generations. PSG/BPSG is mostly replaced by HARP/FCVD at advanced nodes but remains important in select applications.
PSG Composition and Reflow Properties
Phosphosilicate glass (PSG) is SiO₂ with 2-8 wt% phosphorus incorporated via LPCVD (using SiH₄ + O₂ + PH₃). Phosphorus dopant lowers the reflow temperature of SiO₂ from >1100°C to 850-950°C by reducing the glass transition temperature (Tg). At reflow temperature, PSG becomes viscous (like honey); capillary forces smooth topography, filling gaps and smoothing surface. Reflow time is 5-30 minutes depending on feature geometry and topography.
BPSG Composition and Dual Dopants
Borophosphosilicate glass (BPSG) contains both boron and phosphorus dopants, typically 2-4 wt% B and 2-4 wt% P. Boron further lowers Tg (additional ~50°C reduction), enabling lower reflow temperature (~850°C vs ~900°C for PSG). BPSG with balanced B:P ratio (1:1 atomic) achieves lowest Tg. However, boron concentration must be controlled: high boron (>5 wt%) causes boron diffusion into underlying doped layers (n+, p+), degrading junction leakage. Typical maximum boron is 3-4 wt%.
Phosphorus Gettering of Mobile Ions
Phosphorus dopant acts as a getter for mobile ions (Na⁺, K⁺, Li⁺) that cause device leakage and reliability issues. Phosphorus forms Si-O-P bridges that trap and neutralize mobile ions, preventing them from migrating to junctions. This gettering function was critical in older technologies (pre-90 nm) where mobile ion contamination was more prevalent. Modern processes have cleaner manufacturing environments and use other gettering strategies (ion implantation, guard rings), reducing PSG/BPSG reliance for gettering.
Viscous Reflow Process
Reflow is performed in a furnace with carefully controlled temperature ramp: (1) ramp to ~600°C over 20 min (pre-drying to remove moisture, which causes bubbling), (2) hold at 850-950°C for 5-30 min (viscous reflow, topography smoothing), (3) cool down over 30-60 min (stress relief). Too-rapid heating causes water vapor evolution (entrapped in glass during deposition), leading to bubble formation and voids. Too-long reflow or high temperature causes dopant migration (P, B diffusion), crystallization (PSG/BPSG transition from amorphous to polycrystalline), and increased etch rate.
BPSG and CMP Interaction
BPSG has lower etch rate in HF than PSG or undoped SiO₂ due to boron incorporation (B-O bonds more stable than Si-O in HF attack). This provides better etch selectivity in HF dips. However, CMP of BPSG is more challenging: the oxide is softer than undoped SiO₂ (due to dopants), leading to higher removal rate and polishing non-uniformity (pattern density dependent). BPSG CMP requires softer pads and lower pressure vs undoped oxide CMP.
Planarization and Gap Fill Mechanism
During reflow, BPSG fills gaps via viscous flow: surface tension gradient drives flow from high points (small radii of curvature, high surface tension) toward low points (gaps, valleys). This fills narrow gaps (down to ~20 nm width) without requiring explicit trench isolation. The mechanism is fundamentally different from HARP (reactive, bottom-up fill) or FCVD (capillary-driven liquid flow). Reflow is isothermal and slow, making it more predictable than HARP but less suitable for high-AR gaps (>5:1).
Thermal Budget and Junction Compatibility
BPSG reflow temperature (850-950°C) is substantial and can cause: (1) boron and phosphorus dopant diffusion into junctions, (2) dopant activation changes (reduced by several percent due to thermal budget), (3) stress relaxation in stressed films, and (4) silicon surface oxidation (thin native oxide grows if O₂ present). For shallow junctions and advanced nodes, this thermal budget is prohibitive. Modern FinFET and gate-all-around processes avoid PSG/BPSG due to thermal budget constraints; they use lower-temperature HARP/FCVD instead.
Applications in Modern CMOS
PSG/BPSG is still used in select applications: (1) analog circuits (where higher operating temperature is tolerable), (2) back-end metal interconnect (lower sensitivity to dopant diffusion), and (3) power devices (higher temperature ratings). For digital logic at advanced nodes, PSG/BPSG is replaced by HARP, FCVD, or air gap.
Crystallization and Reliability
After reflow, BPSG is initially amorphous. However, at elevated temperature during device operation (e.g., 125°C) or in subsequent anneals, BPSG can crystallize (transition to cristobalite or other phases), changing electrical properties and introducing grain boundaries. Crystallization can degrade leakage characteristics and increase etch rate. Preventing crystallization requires: lower dopant concentration, rapid cooldown after reflow, and lower operating temperature.
Comparison with HARP and Modern Gap Fill
HARP (high-aspect-ratio process) using O₃-TEOS SACVD achieves superior gap fill vs BPSG (AR >6:1 vs AR <3:1 for BPSG reflow) without thermal budget penalty. HARP has replaced BPSG for most interlayer dielectric and gap fill applications. However, BPSG remains relevant for specialized applications requiring thermal planarization and gettering.
Summary
PSG and BPSG dielectrics represent an older paradigm of gap-fill and planarization via thermal reflow, now mostly replaced by cooler, higher-performance HARP and FCVD processes. However, their unique combination of gap-fill capability and gettering function ensures continued niche use in analog, RF, and power device applications.