Photomask Technology covers the design, fabrication, and qualification of the master templates (reticles/masks) used in lithographic patterning — with EUV masks representing the most technically demanding masks ever manufactured, requiring defect-free multilayer reflective blanks, precision absorber patterning, and pellicle protection for manufacturing chips at the most advanced technology nodes.
DUV vs. EUV Mask Comparison:
DUV Mask (transmissive): EUV Mask (reflective):
Light passes through Light reflects off mask
Quartz substrate Low-TEC glass substrate
Chrome absorber TaN/Ru absorber
4×/5× demagnification 4× demagnification
Phase-shift variants No phase-shift (yet)
Binary or attenuated PSM Binary absorber
EUV Mask Architecture:
<svg viewBox="0 0 603 302" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="603" height="302" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,"Liberation Mono",monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#6e7681">┌─────────────────────────┐</tspan><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> Capping layer (2.5nm Ru)</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Mo/Si multilayer </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> 40 pairs of Mo(2.8nm)/Si(4.1nm)</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> (reflective Bragg </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Total: ~280nm</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> mirror, ~67% R) </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Reflects 13.5nm EUV light</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#6e7681">├─────────────────────────┤</tspan></text><text xml:space="preserve" x="20" y="126.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Low-TEC glass substrate</tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">←</tspan><tspan fill="#c9d1d9"> Ultra-low thermal expansion</tspan></text><text xml:space="preserve" x="20" y="145.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> (6.35mm thick, 152mm) </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> coefficient (0±5 ppb/K)</tspan></text><text xml:space="preserve" x="20" y="164.7"><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> </tspan><tspan fill="#6e7681">│</tspan><tspan fill="#c9d1d9"> Flatness: <50nm P-V (post-chucking)</tspan></text><text xml:space="preserve" x="20" y="183.7"><tspan fill="#6e7681">└─────────────────────────┘</tspan></text><text xml:space="preserve" x="20" y="202.7"></text><text xml:space="preserve" x="20" y="221.7"><tspan fill="#c9d1d9">Absorber pattern (on top of multilayer):</tspan></text><text xml:space="preserve" x="20" y="240.7"><tspan fill="#c9d1d9"> Material: TaN (~60-70nm thick) or new high-k absorbers</tspan></text><text xml:space="preserve" x="20" y="259.7"><tspan fill="#c9d1d9"> High-k absorbers (Ni, Ta/Te compounds): improved contrast,</tspan></text><text xml:space="preserve" x="20" y="278.7"><tspan fill="#c9d1d9"> thinner film </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> reduced mask 3D effects (shadowing)</tspan></text></g></svg>
EUV Mask Blank Manufacturing:
1. Substrate preparation: High-purity low-TEC quartz glass (AGC, Schott — only 2 suppliers worldwide), polished to <0.15nm RMS roughness 2. Multilayer deposition: Ion beam deposition (IBD) of 40× Mo/Si bilayers — each layer must have <0.02nm thickness uniformity across 152mm. One defect in any layer → mask blank rejected 3. Capping: 2.5nm Ru protects the multilayer from oxidation 4. Defect inspection: Detect any particle, pit, or multilayer defect >20nm. Yield of defect-free blanks is the major cost driver ($100K+ per blank)
Mask Patterning Process:
1. Deposit absorber film (TaN) on multilayer blank 2. Spin resist → e-beam direct write (multi-beam MBMW — 262K beamlets for throughput) 3. Develop and etch absorber (Cl₂/O₂ plasma) with <0.5nm CD uniformity 4. Clean → defect inspection → repair (AFM-based nanomachining or e-beam induced deposition) 5. Final inspection + registration measurement + pellicle mounting
Write Time: An advanced EUV mask takes 6-20+ hours to write on multi-beam e-beam tools. Curvilinear features from ILT/OPC add pattern complexity.
Mask 3D Effects:
At EUV wavelengths, the ~60nm thick absorber causes significant shadowing and interference effects because the oblique illumination angle (6° chief ray) interacts with the finite absorber height. This causes: CD asymmetry for horizontal vs. vertical features, best-focus shift, and pattern-dependent imaging errors. Mitigation: thin high-k absorbers (<40nm), mask 3D-aware OPC, and etched multilayer (phase-shift) masks.
Cost and Lead Time:
A single EUV mask costs $300K-$500K+. A complete mask set for an advanced node has 80-100+ layers (some DUV, some EUV), costing $15-20M+ total. Lead time: 2-4 months for initial mask set. This cost drives the economic importance of mask re-use, mask optimization, and multi-project wafer (MPW) shuttles.
Photomask technology is the most precise large-area patterning discipline in existence — creating the master templates that define every transistor, wire, and via on a chip, where a single nanometer-scale defect on one mask can be replicated across millions of chips, making mask quality the ultimate guarantor of semiconductor manufacturing yield.
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