Chip Floorplanning is the critical early-stage physical design activity that determines the spatial arrangement of major functional blocks (hard macros, soft macros, memory arrays, analog blocks, I/O rings) on the die — establishing the physical architecture that constrains all subsequent placement, routing, clock distribution, and power delivery, where a good floorplan can mean the difference between timing closure in days versus weeks of iterative optimization.

Why Floorplanning Matters

Floorplanning occurs before standard cell placement but determines its success. Placing two heavily communicating blocks on opposite sides of the die creates long interconnect that no amount of placement optimization can fix. Misplacing a large memory macro can block critical routing channels. The floorplan is the physical architecture — changing it late in the flow is extremely expensive.

Floorplan Elements

• Die Size and Aspect Ratio: Set by package constraints, target utilization (typically 70-80%), and cost targets. Area directly maps to manufacturing cost.
• I/O Ring and Pad Placement: I/O cells arranged along the die periphery (or in area-array for flip-chip). Pad placement is constrained by package ball map and signal assignment.
• Hard Macro Placement: SRAMs, PLLs, ADCs, and other pre-characterized blocks placed first. Orientation, spacing, and proximity to I/O are critical. Memory macros often placed along edges to leave the core area for standard cell logic.
• Power Domain Regions: Each UPF power domain occupies a contiguous region. Power switches, isolation cells, and always-on buffers are placed at domain boundaries.
• Routing Blockages and Channels: Reserve routing channels between macros. Partial blockages limit routing density in congested areas. Keep-out zones prevent standard cells from obstructing macro pin access.

Floorplan Optimization Objectives

Hierarchical Floorplanning

For large SoCs (>100M gates), the design is partitioned into physical hierarchies. Each hierarchy has its own sub-floorplan, developed by separate teams. Interface timing budgets (ILMs — Interface Logic Models) are exchanged between hierarchies to enable concurrent development. Top-level floorplanning assigns die regions to each hierarchy and defines the inter-hierarchy routing channels.

Chip Floorplanning is the physical architecture decision that sets the ceiling for every downstream implementation step — establishing the spatial relationships that determine whether timing, power, and routability targets can be met within schedule and resource constraints.