Physical Design Floorplanning is the critical early-stage physical implementation step that defines the chip's spatial organization by determining die size, placing hard macro blocks, establishing power grid topology, and partitioning the design into regions—setting the foundation that determines the success or failure of all subsequent place-and-route stages.

Die Size and Aspect Ratio:

• Area Estimation: total die area calculated from standard cell area (gate count × average cell area), macro area (memories, PLLs, IOs), and target utilization (60-80%)—margins added for power routing, clock tree, and unforeseen congestion
• Aspect Ratio Selection: typically 1:1 to 1:1.5 for balanced wire distribution—elongated dies increase wirelength on long-axis paths and complicate power grid design
• Package Compatibility: die dimensions must fit within package cavity constraints and match bump/ball pitch requirements—flip-chip designs require die size to accommodate the C4 bump array with 100-200 μm pitch
• Yield Consideration: larger dies have exponentially lower yield due to random defect density—a 10% increase in die area can reduce yield by 15-25% at typical defect densities

Macro Placement Strategy:

• Memory Placement: large SRAM/ROM macros placed along die periphery or in dedicated columns—memory macros are rectangular with fixed pin locations that constrain orientation to 0° or 180° rotation
• Analog Block Isolation: PLLs, ADCs, DACs, and other analog macros placed in corners or edges with dedicated power domains and guard rings to minimize digital switching noise coupling
• Channel Planning: routing channels between macros must be wide enough for signal and power routing—minimum channel width estimated from pin density and routing layer availability
• Macro Orientation: pin-facing optimization ensures macro I/O pins face the logic they connect to, minimizing routing detours—improper orientation can add 20-50% wirelength to critical paths

Power Grid Planning:

• Power Strap Architecture: VDD/VSS straps on upper metal layers defined during floorplanning—strap width, spacing, and layer assignment determined by current density analysis and IR drop budget
• Bump/Pad Assignment: C4 bump or wire-bond pad locations for VDD, VSS, and I/O signals assigned during floorplanning—power bumps typically consume 40-60% of total bump count
• Power Domain Partitioning: multi-voltage domains physically separated with level shifters and isolation cells placed at domain boundaries—each domain requires independent power switch and always-on control logic placement
• Decap Placement: dedicated decoupling capacitor cells inserted in available whitespace during floorplanning—initial placement refined during post-route IR drop analysis

Hierarchical Floorplanning:

• Block-Level Partitioning: large SoCs divided into 10-50 hierarchical blocks, each floorplanned and implemented independently—block boundaries defined by logical function and physical proximity
• Interface Planning: block-to-block interfaces defined with feedthrough pin locations at block boundaries—interface timing budgets (input/output delays) allocated during floorplanning
• Top-Level Integration: blocks treated as hard macros at the top level—top-level floorplan focuses on inter-block routing, global clock distribution, and I/O ring placement

Physical design floorplanning is often considered the most intellectually demanding step in the implementation flow, requiring deep understanding of circuit architecture, power distribution, signal timing, and manufacturing constraints—a well-crafted floorplan can mean the difference between a design that closes timing easily and one that requires months of additional effort.