Physical Design Place and Route — Physical design transforms gate-level netlists into geometric layouts suitable for semiconductor fabrication, encompassing placement of standard cells and routing of interconnections while satisfying timing, power, and manufacturability constraints.

Placement Optimization Strategies — Cell placement fundamentally determines design quality:

• Global placement distributes cells across the chip area using analytical or partitioning-based algorithms that minimize total wirelength while respecting density constraints
• Detailed placement refines cell positions through local swapping, mirroring, and shifting to optimize timing-critical paths and reduce routing congestion
• Timing-driven placement prioritizes critical path cells, clustering them to minimize interconnect delay and enabling synthesis timing targets to be preserved through implementation
• Congestion-aware placement identifies routing hotspots early and redistributes cells to prevent unroutable regions that would require costly iterations
• Multi-voltage domain placement respects power domain boundaries, ensuring level shifters and isolation cells are positioned at domain interfaces correctly

Routing Architecture and Methodology — Interconnect routing connects placed cells through metal layers:

• Global routing assigns net segments to routing regions (G-cells) establishing coarse routing topology while balancing resource utilization across the chip
• Detailed routing determines exact metal track assignments, via placements, and wire geometries within each G-cell following design rule constraints
• Track assignment bridges global and detailed routing by pre-assigning critical nets to specific metal tracks for improved timing predictability
• Multi-cut via insertion replaces single-cut vias with redundant contacts to improve yield and electromigration resistance at minimal area cost
• Non-default routing rules (NDRs) apply wider widths and increased spacing to clock nets and critical signals for reduced resistance and improved noise immunity

Design Rule Compliance — Physical layouts must satisfy foundry manufacturing rules:

• Design rule checking (DRC) validates minimum width, spacing, enclosure, and density requirements for every metal and via layer
• Layout versus schematic (LVS) confirms that the physical layout electrically matches the intended schematic netlist connectivity
• Antenna rule checking identifies process-induced charge accumulation on long metal segments that could damage thin gate oxides during fabrication
• Metal density filling adds dummy metal shapes to meet minimum and maximum density requirements for chemical mechanical polishing (CMP) uniformity
• Via density and coverage rules ensure reliable inter-layer connections across the entire design area

Physical Verification and Signoff — Final verification ensures manufacturing readiness:

• Parasitic extraction (PEX) generates accurate RC models of routed interconnects for post-route timing and signal integrity analysis
• IR drop analysis verifies that power grid resistance does not cause excessive voltage drops at any cell location under worst-case switching activity
• Chip finishing adds pad ring connections, seal rings, alignment marks, and other structures required for packaging and testing
• GDSII or OASIS format generation produces the final mask data submitted to the foundry for photomask fabrication

Physical design place and route represents the critical implementation phase where abstract logic becomes tangible silicon geometry, requiring sophisticated algorithms and iterative optimization to achieve timing closure while meeting all manufacturing requirements.