Physical synthesis is the design methodology that performs logic optimization simultaneously with physical placement information — making timing-driven logic transformations (gate sizing, buffering, restructuring) with knowledge of actual wire lengths and parasitics, rather than using abstract wire load models.

Why Physical Synthesis?

• Traditional Flow: Logic synthesis (using wire load models) → placement → routing → timing analysis. The problem: wire load models are inaccurate estimates — actual wire delays after placement can differ significantly from predictions.
• Physical Synthesis: Combines synthesis and placement — logic optimization decisions are made with knowledge of actual (or estimated actual) wire lengths. Result: much better timing correlation between synthesis and final layout.

Physical Synthesis Optimizations

• Gate Sizing: Increase or decrease the drive strength of gates based on their actual load (wire + pin capacitance). Upsize gates driving long wires; downsize gates driving short wires.
• Buffer Insertion: Add buffers to break long nets into segments with acceptable delay. Placement-aware buffering knows exactly where to place buffers for optimal delay.
• Logic Restructuring: Reorganize the logic netlist to improve timing — for example, move critical logic closer to the receiving flip-flop, or decompose large gates into smaller stages.
• Pin Swapping: Swap logically equivalent pins on a gate to improve wire routing and reduce delay.
• Cell Replication: Duplicate a high-fanout cell and distribute its load — reduces individual wire lengths.
• Logic Cloning: Clone logic cones to reduce wire length to distant loads.

Physical Synthesis in the Design Flow

• In-Place Optimization (IPO): After initial placement, perform logic optimization with actual placement data. Iterates between optimization and placement refinement.
• Post-Route Optimization: After routing, further optimize timing using extracted (actual) parasitics — the most accurate timing data available.
• Concurrent Optimization: Modern tools (Innovus, ICC2) perform placement and optimization concurrently — every optimization move is immediately evaluated with placement-based timing.

Physical Synthesis vs. Pure Synthesis

• Pure Synthesis (Design Compiler, Genus without placement): Uses statistical wire load models (WLMs) to estimate wire delay. Can be significantly wrong — especially for long wires or irregular floorplans.
• Physical Synthesis: Uses actual placement distances to estimate wire delay. Typically 20–30% better timing correlation with final layout compared to WLM-based synthesis.
• Post-Placement Optimization: The most common form of physical synthesis — logic optimization happens after cells are placed.

Benefits

• Better Timing: More realistic wire delay estimation leads to better optimization decisions.
• Fewer Iterations: Reduced gap between synthesis and P&R timing reduces the number of design iterations needed for timing closure.
• Area Efficiency: No over-optimization of paths that turn out to have short wires, and proper optimization of paths with long wires.

Physical synthesis is the modern standard for digital implementation — the days of fully abstract synthesis followed by physical design are over, replaced by integrated flows where logic and layout are optimized together.