Physical Verification (DRC/LVS) Flow is the mandatory signoff step in chip design where the final layout is checked against foundry design rules (DRC) and verified to match the intended schematic connectivity (LVS), ensuring the layout is both manufacturable and functionally correct before tapeout.
Physical verification is the last line of defense before committing a design to multi-million-dollar mask fabrication. Any error that escapes this step results in silicon failure.
Design Rule Check (DRC):
DRC verifies that every geometric shape in the layout conforms to the foundry's manufacturing rules. These rules encode the physical limitations of lithography, etching, deposition, and CMP processes.
| Rule Category | Examples | Purpose |
|--------------|---------|----------|
| Minimum width | Metal1 >= 28nm | Printability, electromigration |
| Minimum spacing | Metal-metal gap >= 32nm | Short prevention, crosstalk |
| Enclosure | Via enclosed by metal >= 10nm | Contact reliability |
| Density | Metal density 20-80% per window | CMP planarity |
| Antenna | Gate area / metal area ratio | Plasma charging protection |
| Multi-patterning | SADP/SAQP coloring legality | Lithographic decomposition |
Modern DRC rule decks at advanced nodes (5nm, 3nm) contain 5000-10000+ individual rules. Run time for a full-chip DRC on a complex SoC can take 12-48 hours on a compute farm. Hierarchical DRC exploits design hierarchy to reduce runtime by 10-100x.
Layout Versus Schematic (LVS):
LVS extracts the circuit netlist from the physical layout (recognizing transistors, resistors, capacitors from geometric patterns) and compares it against the schematic netlist. Mismatches indicate wiring errors, missing connections, or unintended shorts.
LVS checks: device recognition (correct transistor W/L extraction), connectivity (nets match between layout and schematic), device parameters (threshold voltage type, well connections), and pin assignment (I/O pins in correct locations).
ERC (Electrical Rule Check): Checks for electrical correctness beyond connectivity — floating gates, unconnected inputs, well tap spacing, ESD path continuity, and latch-up prevention (sufficient substrate/well taps). PERC (P&R Electrical Rule Check) extends ERC to power-aware verification: checking level shifters at voltage domain boundaries, isolation cells for power-gated domains, and always-on signal paths.
Foundry Signoff Requirements: Foundries require clean DRC, LVS, ERC, and antenna checks using their certified tool versions (typically Synopsys IC Validator or Siemens Calibre). Any waived violations must be formally documented with foundry approval. Metal fill (dummy fill for density) must be inserted and verified before final DRC signoff.
Physical verification is the non-negotiable quality gate in chip design — no amount of functional verification, timing closure, or power optimization matters if the layout cannot be manufactured correctly, making DRC/LVS clean status the ultimate prerequisite for tapeout.