<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Place &amp; route: turn a gate-level netlist into a manufacturable layout</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Decide where every cell sits, then wire them on the metal stack &#8212; all while meeting timing</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Floorplan &amp; placement</text><text x="32" y="106" fill="#8b949e" font-size="10.5">macros pinned, cells packed in rows</text><rect x="42" y="118" width="182" height="140" rx="3" fill="#111a24" stroke="#30363d"/><!-- IO ring --><g fill="#3f9d6f"><rect x="48" y="122" width="6" height="6"/><rect x="70" y="122" width="6" height="6"/><rect x="92" y="122" width="6" height="6"/><rect x="114" y="122" width="6" height="6"/><rect x="136" y="122" width="6" height="6"/><rect x="158" y="122" width="6" height="6"/><rect x="180" y="122" width="6" height="6"/><rect x="202" y="122" width="6" height="6"/></g><!-- macros --><rect x="50" y="136" width="52" height="44" rx="2" fill="#38506a"/><text x="76" y="161" fill="#cfe4f5" font-size="8" text-anchor="middle">SRAM</text><rect x="164" y="204" width="54" height="46" rx="2" fill="#38506a"/><text x="191" y="230" fill="#cfe4f5" font-size="8" text-anchor="middle">macro</text><!-- std cell rows --><g fill="#34d399" opacity="0.55"><rect x="110" y="138" width="106" height="8"/><rect x="110" y="150" width="106" height="8"/><rect x="110" y="162" width="106" height="8"/><rect x="50" y="188" width="106" height="8"/><rect x="50" y="200" width="106" height="8"/><rect x="50" y="212" width="106" height="8"/><rect x="50" y="224" width="106" height="8"/><rect x="50" y="236" width="90" height="8"/></g><text x="133" y="274" fill="#8b949e" font-size="8.5" text-anchor="middle">standard cells fill the rows between macros</text><text x="32" y="296" fill="#adb5bd" font-size="9.5">Placement chooses an (x,y) for every</text><text x="32" y="311" fill="#adb5bd" font-size="9.5">cell to shorten wires and hit timing,</text><text x="32" y="326" fill="#adb5bd" font-size="9.5">while leaving room to route and</text><text x="32" y="341" fill="#adb5bd" font-size="9.5">spreading heat and power draw evenly.</text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; Routing the metal stack</text><text x="279" y="106" fill="#8b949e" font-size="10.5">layers alternate direction, vias connect</text><rect x="287" y="118" width="196" height="120" rx="3" fill="#111a24" stroke="#30363d"/><!-- horizontal tracks --><g stroke="#38bdf8" stroke-width="2"><line x1="295" y1="132" x2="475" y2="132"/><line x1="295" y1="152" x2="475" y2="152"/><line x1="295" y1="172" x2="475" y2="172"/><line x1="295" y1="192" x2="475" y2="192"/><line x1="295" y1="212" x2="475" y2="212"/></g><!-- vertical tracks --><g stroke="#a99cf0" stroke-width="2" opacity="0.9"><line x1="320" y1="126" x2="320" y2="230"/><line x1="360" y1="126" x2="360" y2="230"/><line x1="400" y1="126" x2="400" y2="230"/><line x1="440" y1="126" x2="440" y2="230"/></g><!-- vias --><g fill="#e0b13a"><circle cx="320" cy="152" r="2.6"/><circle cx="400" cy="132" r="2.6"/><circle cx="360" cy="192" r="2.6"/><circle cx="440" cy="212" r="2.6"/></g><text x="300" y="252" fill="#38bdf8" font-size="8">&#8212; horizontal (Mx)</text><text x="392" y="252" fill="#a99cf0" font-size="8">| vertical (My)</text><text x="300" y="266" fill="#e0b13a" font-size="8">&#9679; via</text><text x="279" y="290" fill="#adb5bd" font-size="9.5">Global routing assigns nets to regions;</text><text x="279" y="305" fill="#adb5bd" font-size="9.5">detailed routing lays exact tracks and</text><text x="279" y="320" fill="#adb5bd" font-size="9.5">vias, layer by layer, with no shorts or</text><text x="279" y="335" fill="#adb5bd" font-size="9.5">spacing violations. Congestion = failure.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; What it optimizes</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the PPA loop, run to signoff</text><circle cx="532" cy="126" r="2.4" fill="#34d399"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Timing</text><text x="542" y="143" fill="#8b949e" font-size="9">close setup &amp; hold on every path; buffer,</text><text x="542" y="156" fill="#8b949e" font-size="9">resize and legalize cells to fix slack.</text><circle cx="532" cy="176" r="2.4" fill="#38bdf8"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Congestion &amp; area</text><text x="542" y="193" fill="#8b949e" font-size="9">keep routing demand under track supply;</text><text x="542" y="206" fill="#8b949e" font-size="9">denser = smaller die, but harder to wire.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Power &amp; IR</text><text x="542" y="243" fill="#8b949e" font-size="9">build the power grid, cap switching power,</text><text x="542" y="256" fill="#8b949e" font-size="9">hold IR-drop within budget.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#f87171" font-size="10" font-weight="700">Iterate to signoff</text><text x="536" y="306" fill="#adb5bd" font-size="9">Place &#8594; route &#8594; analyze timing/DRC &#8594;</text><text x="536" y="320" fill="#adb5bd" font-size="9">engineering-change-order fixes &#8594; repeat</text><text x="536" y="334" fill="#adb5bd" font-size="9">until the layout is DRC-clean and every</text><text x="536" y="348" fill="#adb5bd" font-size="9">corner meets timing. Then tape-out.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Placement</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Where each cell sits &#8212; sets wire</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">length, timing and routability.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Routing</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">Wire the nets across metal layers</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">and vias with zero DRC violations.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#e0b13a" font-size="11" font-weight="700">Timing closure</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">The loop that makes every path meet</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">its clock &#8212; the hard part of P&amp;R.</text></svg>

Place and Route (PnR) — the automated process of positioning millions to billions of standard cells and connecting them with metal wires to create the physical chip layout.

Placement

1. Global Placement: Distribute cells across the floorplan to minimize estimated wire length 2. Legalization: Snap cells to legal row positions (standard cell rows) 3. Detailed Placement: Fine-tune positions to optimize timing and congestion

Clock Tree Synthesis (CTS)

• Build balanced clock distribution network
• Goal: Minimize clock skew (arrival time difference between registers) to < 50ps
• Techniques: H-tree, mesh, or hybrid topologies with buffers and inverters

Routing

1. Global Routing: Plan approximate wire paths (which routing channels to use) 2. Detailed Routing: Determine exact wire geometry on metal layers, respecting design rules 3. DRC-clean routing: Fix any spacing, width, or via violations

Optimization Iterations

• Fix setup violations: Upsize drivers, add buffers, reroute
• Fix hold violations: Insert delay buffers
• Fix congestion: Move cells, spread logic
• Fix IR drop: Widen power stripes, add vias

Tools: Synopsys ICC2, Cadence Innovus, Synopsys Fusion Compiler

PnR transforms the abstract netlist into a physical layout ready for manufacturing — the culmination of the design flow.