Place and route (P&R) is the physical-design step that takes the gate-level netlist from synthesis and gives it a concrete form on the die: it decides where every standard cell and macro physically sits, builds the network that distributes the clock, and draws the metal wires that connect everything — all while meeting timing, power, and manufacturability rules. Tools like Cadence Innovus, Synopsys IC Compiler II, and the open-source OpenROAD perform this translation, turning a logical netlist into the layout (GDSII/OASIS) the foundry actually manufactures.\n\nIt proceeds in stages: floorplan, placement, clock tree, routing. Floorplanning comes first, fixing the die size, placing the large hard macros (memories, PLLs, IP blocks) and the I/O, and defining the power-delivery grid. Placement then positions the millions of standard cells into rows, clustering connected logic together to keep wires short. Clock-tree synthesis (CTS) builds a balanced, buffered network so the clock edge reaches every flip-flop with minimal skew. Finally routing draws the actual metal interconnect across many layers, connecting cell pins while obeying the foundry's design rules. Each stage is followed by timing-driven optimization before the next begins.\n\nEvery stage is driven by timing, congestion, and physical rules. Because wire delay dominates gate delay at advanced nodes, the P&R tool estimates timing continuously and reshapes placement and routing to close the clock — buffering long nets, resizing and cloning cells, and legalizing positions onto the grid. Routing must avoid congestion (too many wires demanding the same region) and honor design-rule constraints on spacing, width, and vias that become brutal at 5nm and 3nm. Power integrity (IR drop) and signal integrity (crosstalk) are checked along the way. The result is a layout that is DRC- and LVS-clean, matches the netlist, and meets the timing constraints.\n\n| Stage | What it decides | Key concern |\n|---|---|---|\n| Floorplan | die size, macro & I/O placement, power grid | area, aspect ratio |\n| Placement | standard-cell locations in rows | wirelength, congestion |\n| CTS | buffered clock network | skew, latency, power |\n| Routing | metal wires across layers | DRC, congestion, SI |\n| Optimize | buffering, resizing, legalization | close timing |\n| Output | GDSII / OASIS layout | DRC / LVS clean |\n\n``svg\n\n``\n\nP&R turns the netlist's promised timing into physical reality. Synthesis only estimated timing with statistical wire-load models; place and route replaces those guesses with real cell positions and extracted parasitics, so this is the stage where a design either genuinely closes timing or reveals that it cannot. The layout it produces feeds signoff directly: static timing analysis on extracted RC parasitics, physical verification (DRC/LVS), and IR-drop and electromigration checks. Getting the floorplan and constraints right is decisive — a poor floorplan creates congestion and long timing paths that no amount of routing effort can rescue, forcing iteration back to synthesis or even the RTL.\n\nRead place and route through a quant lens rather than a 'lay out the chip' lens: the tool is minimizing wirelength while closing a hard timing constraint over the physical positions of millions of cells, and interconnect delay — not gate delay — is the currency it spends. Every lever (floorplan aspect ratio, macro placement, cell density, how many routing layers) moves congestion and wire delay together, so the craft is arranging logic so that the critical register-to-register paths stay physically short. At advanced nodes the placement, not the gates, is what decides whether the clock closes — which is why physical synthesis now folds placement back into synthesis itself.