Place and Route (PnR) — the automated process of positioning millions to billions of standard cells and connecting them with metal wires to create the physical chip layout.

Placement

1. Global Placement: Distribute cells across the floorplan to minimize estimated wire length 2. Legalization: Snap cells to legal row positions (standard cell rows) 3. Detailed Placement: Fine-tune positions to optimize timing and congestion

Clock Tree Synthesis (CTS)

• Build balanced clock distribution network
• Goal: Minimize clock skew (arrival time difference between registers) to < 50ps
• Techniques: H-tree, mesh, or hybrid topologies with buffers and inverters

Routing

1. Global Routing: Plan approximate wire paths (which routing channels to use) 2. Detailed Routing: Determine exact wire geometry on metal layers, respecting design rules 3. DRC-clean routing: Fix any spacing, width, or via violations

Optimization Iterations

• Fix setup violations: Upsize drivers, add buffers, reroute
• Fix hold violations: Insert delay buffers
• Fix congestion: Move cells, spread logic
• Fix IR drop: Widen power stripes, add vias

Tools: Synopsys ICC2, Cadence Innovus, Synopsys Fusion Compiler

PnR transforms the abstract netlist into a physical layout ready for manufacturing — the culmination of the design flow.