Home Knowledge Base The plasma exists only because external RF power continuously replaces the energy that electrons lose in every inelastic collision.

A semiconductor plasma is a weakly ionized gas where fewer than 1 in 300 particles carry charge — yet those few charged particles control 40–50% of all processing steps in a modern fab because the plasma sustains a 75$\times$ temperature imbalance: electrons at $3$ eV ($34{,}800$ K) break Si–Si bonds (2.3 eV), C–F bonds (5.0 eV), and ionize argon (15.8 eV), while the background gas stays near 400 K so the wafer never exceeds the 50–400$^\circ$C range that its existing structures can survive.

RF/microwave power (10 W – 100 kW) → free electrons absorb energy → electrons collide with gas molecules → ionization (creates ions + more electrons), dissociation (creates reactive radicals), excitation (creates photons) → ions accelerated through sheath → directional bombardment at wafer → radicals diffuse isotropically → volatile etch products / deposited film → pump exhaust
Semiconductor Plasma: Non-Equilibrium is the Point Electrons at 35,000 K break bonds; gas at 400 K keeps the wafer alive Temperature Electrons 34,800 K 75x Ions 464 K Gas 400 K Wafer 50-400°C What Each Temperature Regime Enables Hot electrons (3 eV) → Ionization: Ar → Ar⁺ + e⁻ (15.8 eV threshold, tail electrons) Dissociation: CF₄ → CF₃ + F (12.5 eV), Cl₂ → 2Cl (2.5 eV) Creates both ions (directional) and radicals (reactive) Cold ions (0.04 eV) accelerated through sheath → Gain 20–500 eV directed energy perpendicular to wafer Arrive at <2° angular spread (ICP) — vertical etching Sputter, break bonds, enhance chemical reactions (synergy) Cold gas + cold wafer → Existing transistors, interconnects, films survive processing No thermal diffusion of dopants (activation energy not reached) No melting of metals (Al mp 660°C, Cu mp 1085°C) Photoresist survives (decomposition >250°C manageable) This temperature hierarchy is impossible in thermal equilibrium — it requires continuous RF power input Remove the power → electrons cool in ~10 ns → plasma extinguishes in ~1 ms

The plasma exists only because external RF power continuously replaces the energy that electrons lose in every inelastic collision. An electron at 3 eV colliding with Cl$_2$ spends 2.5 eV to dissociate the molecule; the resulting 0.5 eV electron must be re-heated by the RF field before it can dissociate another molecule. At $5 \times 10^{11}$ cm$^{-3}$ density, each cubic centimeter contains $5 \times 10^{11}$ electrons each losing $\sim$3 eV every 10 ns (mean collision time), requiring a power input of $5 \times 10^{11} \times 3 \times 1.6 \times 10^{-19} / (10^{-8}) \approx 24$ W/cm$^3$ just to maintain the electron temperature. The actual absorbed power density in an ICP at 1 kW over a 300 mm $\times$ 10 mm skin volume of 700 cm$^3$ is $\sim$1.4 W/cm$^3$ — the difference reflects that only tail electrons above threshold participate in ionization, and most energy goes into elastic heating of the gas.

Every plasma process in semiconductor manufacturing exploits the same trick: electrons do the chemistry while ions provide the directionality. In etch, radicals adsorb on exposed surfaces and ions break the bonds beneath them (Coburn–Winters synergy, 10$\times$ rate enhancement). In PECVD, radicals deposit film at 300–400$^\circ$C that thermal CVD would require 700–900$^\circ$C to achieve — enabling deposition over aluminum interconnects. In PVD, ions sputter atoms from a target and those atoms condense on the wafer. In plasma-enhanced ALD, brief plasma pulses provide the reactive species that complete each monolayer cycle without thermal activation. In ion implantation, the plasma serves as an ion source; extraction optics then accelerate selected species to 1–100 keV.

The four operational knobs that control a semiconductor plasma are pressure, power, frequency, and gas composition — and each maps to a different physical effect. Pressure sets the collision rate (mean free path ranges from 0.3 mm at 200 mTorr to 60 mm at 1 mTorr) and determines whether the sheath is collisional or collisionless. Power sets the electron density ($10^9$–$10^{12}$ cm$^{-3}$) and therefore the ion flux ($10^{14}$–$10^{17}$ cm$^{-2}$ s$^{-1}$). Frequency determines the electron heating mechanism: at 13.56 MHz ohmic and stochastic heating dominate; at 2.45 GHz (microwave) resonant cyclotron absorption provides nearly 100% coupling. Gas composition determines which bonds break and which radicals form — Cl$_2$ for silicon, C$_4$F$_8$ for oxide, O$_2$ for organics.

Quasi-neutrality holds everywhere except in the sheath — a region only 182 $\mu$m to 5 mm thick that concentrates the full DC voltage drop and accelerates every ion toward the wafer. The Debye length at $5 \times 10^{11}$ cm$^{-3}$ is 182 $\mu$m — $1{,}600\times$ smaller than the 300 mm chamber. Bulk plasma is electrically neutral to better than $10^{-5}$ relative charge imbalance. But at every surface, electrons escape faster than ions, charging the surface negative until a retarding potential (the plasma potential, typically 15–25 V) builds to confine electrons. When external RF bias adds 20–500 V, the sheath expands to 2–5 mm, and every ion crosses it in the directed normal direction. This sheath is the entire mechanism by which plasma delivers directional processing to a wafer.

The plasma equipment market exceeds 38 billion USD annually — roughly 60% of all wafer fab equipment — split across etch (18B), deposition (15B), implant (3B), and strip (2B). Lam Research, Applied Materials, Tokyo Electron, and Hitachi High-Tech dominate etch. Applied Materials and Lam dominate CVD/PVD. Applied Materials dominates implant (Varian division). A single advanced logic fab at the 2 nm node purchases 2–4 billion USD of plasma equipment, running 200–400 plasma chambers in its etch bay alone and processing each wafer through 100–200 plasma steps from front-end transistor formation through back-end interconnect completion. The installed base worldwide exceeds 100,000 plasma process chambers operating continuously in three-shift production.

At the 2 nm gate-all-around nanosheet node, plasma processes face atomic-scale limits: a single misplaced ion or one monolayer of unintended etching equals a failed device. The nanosheet channel is 5 nm thick — roughly 25 atomic layers of silicon. The inner spacer etch must remove SiGe to $\pm$0.3 nm precision without attacking the Si channel. The gate metal fill requires conformal plasma ALD of work-function metals (TiN, TiAlC) at sub-angstrom thickness control. Edge placement error budget allocates only $\pm$0.5 nm total across litho, etch, and deposition — meaning each plasma step must contribute less than $\pm$0.2 nm. Achieving this at 300 mm wafer scale with 100+ plasma steps per wafer is the central manufacturing challenge of the current decade.

ApplicationPressureDensity (cm$^{-3}$)Ion EnergyKey Species
ICP etch2–20 mTorr$10^{11}$–$10^{12}$20–500 eVCl, F, CF$_x$, Ar$^+$
CCP/RIE etch50–200 mTorr$10^9$–$10^{10}$200–800 eVSame + broad IADF
PECVD0.5–10 Torr$10^9$–$10^{10}$10–50 eVSiH$_4$, NH$_3$, N$_2$O
PVD/sputter1–10 mTorr$10^{10}$–$10^{11}$300–1000 eVAr$^+$, metal atoms
Plasma ALD1–10 Torr$10^{10}$10–30 eVO, N, H radicals
Ion implant source0.5–5 mTorr$10^{11}$–$10^{12}$1–100 keV (extracted)B$^+$, P$^+$, As$^+$

Read semiconductor plasma through a non-equilibrium temperature hierarchy lens rather than an ionized gas lens: the entire value of plasma processing rests on the 75$\times$ electron-to-ion temperature ratio that lets electrons break bonds while the wafer stays cold — and every equipment architecture (ICP, CCP, ECR, helicon, microwave) is a different engineering solution to the same problem of sustaining that temperature imbalance at the density, uniformity, and reproducibility that manufacturing demands.

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