Plasma Nitridation of Gate Dielectrics is the CMOS process technique that incorporates nitrogen atoms into silicon dioxide or high-k gate dielectric films using a nitrogen plasma — increasing the dielectric constant (raising capacitance without increasing physical thickness), blocking boron penetration from polysilicon or metal gates, and improving the dielectric's resistance to hot carrier degradation and bias temperature instability, making it an essential step in both legacy SiON and advanced high-k/metal-gate process flows.
Why Nitrogen in Gate Dielectric
- SiO₂ dielectric: k=3.9 → too thin at advanced nodes → tunneling leakage.
- Add nitrogen: SiON has k=4.5-6.0 → same capacitance with thicker physical film → less leakage.
- Boron penetration: p-type poly gate → B atoms diffuse through thin SiO₂ → shifts Vt.
- Nitrogen blocks boron: N atoms in oxide create diffusion barrier → stable Vt.
- Reliability: Nitrogen improves resistance to NBTI and hot carrier injection.
Decoupled Plasma Nitridation (DPN)
- Most widely used method for gate dielectric nitridation.
- Decoupled: Plasma generation separated from wafer → ions have low energy → minimal damage.
- Process: N₂ plasma at 10-100 mTorr → nitrogen radicals and ions bombard dielectric surface.
- Temperature: Room temperature to 400°C (low thermal budget).
- Result: Nitrogen concentration peaks at dielectric surface (5-15 at%) → graded profile.
Nitrogen Incorporation Profiles
| Method | N Profile | Peak N% | Damage | Use Case |
|--------|-----------|---------|--------|----------|
| DPN (decoupled plasma) | Surface-peaked | 10-20% | Low | Standard CMOS |
| Remote plasma | Uniform | 5-10% | Very low | High-k pre-treatment |
| Thermal (NH₃ anneal) | Interface | 3-8% | None | Legacy, low-k dielectric |
| Slot plane antenna (SPA) | Surface | 8-15% | Very low | Advanced nodes |
Post-Nitridation Anneal (PNA)
- After DPN: Nitrogen atoms not fully bonded → interface traps remain.
- PNA: Anneal in O₂ or N₂O at 900-1050°C for 5-30 seconds.
- Purpose: Heal plasma damage, drive nitrogen deeper, remove excess N at interface.
- Interface: Too much N at Si/SiO₂ interface → increased Dit (interface traps) → mobility degradation.
- PNA optimizes N profile: Pushes N away from interface toward bulk → best combination of capacitance + mobility.
Nitrogen in High-k/Metal-Gate
- Even with HfO₂ high-k: Thin SiO₂ interfacial layer (IL) exists between Si and HfO₂.
- Nitridation of IL: Increases IL k-value → thinner EOT.
- Nitrogen in HfO₂: DPN of HfO₂ surface → blocks oxygen vacancy diffusion.
- But excess N: Degrades PBTI (positive bias temperature instability) in NMOS.
- Balance: 5-10% N in IL, minimal N in HfO₂ bulk.
Process Control
| Parameter | Impact | Control Method |
|-----------|--------|---------------|
| Plasma power | N dose (higher power = more N) | RF power setpoint |
| Exposure time | N dose and depth | Process time |
| Chamber pressure | N energy and profile shape | Throttle valve |
| Post-anneal temperature | N profile redistribution | RTP recipe |
| N₂ flow rate | Plasma density | Mass flow controller |
Plasma nitridation is the gate dielectric engineering technique that extended SiO₂-based gates by two technology generations and continues to enable EOT scaling in high-k stacks — by precisely controlling where and how much nitrogen is incorporated into the dielectric, manufacturers simultaneously improve capacitance, block dopant penetration, and enhance reliability, making nitridation one of the most impactful single-step process improvements in CMOS transistor history.