Poly Open CMP (POC) is the chemical mechanical planarization step in the replacement metal gate (RMG/gate-last) process flow that removes the dielectric overburden deposited over the dummy poly gate to expose the top of the poly gate for subsequent replacement — a precision CMP step where stopping exactly at the poly surface (neither over-polishing into the poly nor leaving residual dielectric) is critical for achieving uniform gate height and consistent device characteristics across the wafer.

POC Role in Gate-Last Flow

1. Poly dummy gate patterned
2. Spacer formation (SiN)
3. S/D implant or epi
4. ILD deposition (e.g., SiO₂ or low-k) — covers everything including poly gates
5. *** POC CMP *** ← This step
   - Remove ILD above poly top → expose poly gate surface
   - Stop precisely at poly — do not over-polish
6. Poly etch (selective remove of poly dummy gate → leaves trench)
7. High-k + metal gate fill (ALD + PVD/CVD)
8. Metal gate CMP (remove metal overburden above gate level)

POC Challenges

• Endpoint: CMP must stop exactly when poly is exposed — too early → ILD cap remains (gate cannot be etched); too late → poly is thinned (gate height non-uniform → device Vt variation).
• Pattern density variation: Dense poly arrays vs. isolated poly → different polish rates → center vs. edge of wafer variation.
• Hard cap materials: Poly gate often capped with SiN or SiO₂ hard mask from poly etch → POC must clear this cap.

POC Process Parameters

Endpoint Detection for POC

• Optical reflectance: Poly surface has different optical reflectance than oxide → change in in-situ reflectance signal → endpoint trigger.
• Motor current: Friction changes when transitioning from oxide to poly → slight current change.
• Time-based with calibration: For uniform films, run calibrated time after endpoint signal.

Gate Height Control

• After POC, gate height = height of poly above S/D level = original poly deposition thickness − CMP removal.
• Gate height variation σ < 5 nm (3σ) required for acceptable Vt uniformity.
• Gate height too low: Gate resistance increases; metal gate fill may not completely fill trench.
• Gate height too high: Aspect ratio for metal gate fill increases → void risk.

Metal Gate CMP after Fill

• After high-k + WF metal + metal fill in the gate trench:
• Second CMP step removes overburden and planarizes metal gate to target height.
• Selectivity: Metal:SiN (cap) or Metal:SiO₂ (ILD) → stop when gate level reached.
• Metal CMP uses different slurry chemistry (lower pH, different abrasive) vs. oxide CMP.

Gate Last CMP at Advanced Nodes (FinFET/GAA)

• FinFET: Poly dummy gate over 3D fin → after POC, poly exposed across fin top AND sidewalls.
• GAA: Dummy poly gate removal exposes nanosheet stack → gate trench is much narrower (8–12 nm) and deeper.
• Gate fill into narrow GAA trench requires extremely well-controlled gate height from POC + metal CMP.

Poly Open CMP is the precision planarization gatekeeper of the replacement metal gate process — by stopping exactly at the dummy poly surface with nanometer-level control, POC enables the uniform gate height that subsequent high-k and metal gate fill steps require to produce consistent transistor threshold voltage and drive current across billions of gates on a modern chip.