CVD polysilicon deposition creates a microstructure, not merely a silicon thickness. A film called “poly” is an evolving population of nuclei, grains, grain boundaries, texture, roughness, defects, stress, and impurities. Precursor chemistry, actual wafer temperature, pressure, surface state, residence time, thickness, doping, and every later anneal decide which population the integration receives.

Begin with the required final state. A gate electrode may prioritize sheet resistance, work function, oxide integrity, and pattern fidelity. A MEMS structural layer adds residual-stress gradient, modulus, fatigue, and release behavior. A resistor needs a controlled dopant–grain-boundary system. A capacitor electrode may intentionally seek high surface area. “Deposit polysilicon” is therefore incomplete until the downstream electrical, mechanical, topographic, and thermal requirements are stated.

LPCVD from silane is the reference route, but not the only silicon chemistry. The simplified net balance is SiH₄ → Si + 2H₂. The actual mechanism passes through adsorption, hydrogen removal, surface diffusion, incorporation, and desorption. Disilane and chlorinated silicon precursors can change activation, nucleation, growth rate, impurity, conformality, delivery, and exhaust burdens. Never transfer a temperature window between chemistries by name alone.

Polysilicon is distinct from epitaxy. On a suitable clean crystalline silicon surface, deposited atoms can inherit substrate registry and grow epitaxially. On amorphous oxide or nitride, no crystal lattice exists to copy, so independent nuclei form with different orientations and impinge. A process that is epitaxial in an opened silicon window may form polycrystalline deposits on surrounding dielectric unless selective chemistry suppresses them.

The amorphous-to-poly boundary is a process region, not a universal thermometer reading. Reported transition temperatures depend on precursor, pressure, growth rate, surface, contamination, thickness, temperature calibration, and the measurement used to call a film crystalline. Near the boundary, a small thermal offset can change incubation, grain density, roughness, and stress dramatically. Specify actual wafer temperature evidence and phase evidence instead of a nominal set point.

Nucleation establishes the later film. Adsorbed silicon-bearing species diffuse, form stable islands, and expand until islands coalesce. Nucleation density controls the initial grain-spacing distribution; coalescence creates boundaries and stress. Sparse nuclei can grow into larger surface features, while dense nuclei often yield a finer initial structure. The relationship is conditional because subsequent competitive growth and annealing can replace the initial distribution.

Polysilicon nucleation incubation is directly measurable. A delayed start on oxide, nitride, native oxide, or a contaminated surface makes thickness nonlinear with deposition time at the beginning of the process. This matters for ultrathin electrodes and liners even when a thick-film rate appears stable. A thickness-versus-time series, surface-sensitive chemistry, and early-stage microscopy reveal incubation better than a single mature film.

The underlying surface participates directly in nucleation chemistry. Hydroxyl density, termination, native oxide, adsorbed water, carbon, plasma damage, roughness, and prior thermal history change adsorption and nucleation. HF-last silicon, thermal oxide, PECVD oxide, silicon nitride, and metal surfaces should not be assumed equivalent. Queue time between preclean and deposition can become a hidden nucleation variable.

Temperature changes several mechanisms at once. It affects precursor decomposition, hydrogen desorption, surface diffusion, nucleation probability, incorporation, gas-phase reaction, and crystallinity. Raising temperature may increase deposition rate in a surface-reaction-limited regime, but rate can become transport-limited or respond differently after precursor depletion becomes important. A rate-versus-temperature plot should be interpreted together with phase and morphology.

Pressure and silane partial pressure reshape transport and nucleation. They set molecular arrival, residence, depletion, and the balance between surface reaction and unwanted gas-phase decomposition. Low pressure supports batch uniformity and surface-dominated growth when the reactor is correctly designed. Excess residence or reactant concentration can create powder, wall deposition, haze, and particles rather than useful wafer throughput.

Flow is not the same as delivered surface flux. Injector geometry, tube conductance, boat loading, wafer spacing, pump speed, wall consumption, and temperature determine what each wafer sees. Recipe sccm alone cannot explain front-to-back variation. Use pressure, flow, load size, wafer area, and axial rate/composition maps as a coupled reactor description.

Grains compete as thickness accumulates. Once nuclei impinge, favorably oriented grains may outgrow others, producing texture and a columnar structure. Grain width and surface relief can therefore change with film thickness even under one constant recipe. A thick-film grain size cannot be assigned to the first tens of nanometers at an interface.

Grain boundaries are functional material. They contain disorder, dangling bonds, segregated dopant and impurities, and fast diffusion paths. They scatter or trap carriers, influence oxidation and silicidation, provide defect-assisted transport, and alter wet/dry etch. Two films with the same crystalline volume fraction can behave differently because their boundary density and boundary chemistry differ.

Electrical resistivity is not determined by dopant dose alone. Carrier activation, grain-boundary barriers, grain size, compensation, hydrogen, and contact resistance all contribute. At lower active carrier density, boundary trapping can dominate conduction; at high doping, barriers may narrow while activation and solid-solubility constraints emerge. Interpret sheet resistance with thickness, Hall or carrier data where appropriate, and the full thermal history.

Undoped deposited polysilicon still acquires an electrical history. Background boron, phosphorus, metals, oxygen, carbon, and memory from previously doped reactor runs can alter resistivity. Furnace sharing between intrinsic and doped recipes requires contamination controls, monitor wafers, clean rules, and sequence qualification. “Undoped” should mean a measured impurity and electrical state, not simply that no dopant gas was commanded.

In-situ doping changes growth itself. Phosphine, diborane, or arsine does more than supply a future carrier: it can inhibit or enhance surface reactions, change incubation, texture, grain size, stress, and roughness. The dopant-to-silicon gas ratio is therefore a deposition knob as well as a concentration knob. Detailed in-situ-doping and gate-poly pages should own those recipe-specific design spaces.

Post-deposition implantation decouples growth and dose, but adds damage and topology constraints. Implant energy and angle set the as-implanted profile; grain channeling and boundary paths can complicate it. Annealing repairs damage, activates dopant, drives diffusion, and evolves grains and stress simultaneously. Thick or high-aspect-ratio structures may be difficult to dope uniformly by line-of-sight implantation.

Annealing can transform a deposited film. Amorphous silicon may nucleate and crystallize; fine-grained poly may undergo grain growth; hydrogen and impurities redistribute; dopants activate and segregate; stress relaxes or reverses. Ramp rate, peak temperature, dwell, ambient, cap, thickness, and underlayer affect the result. “Annealed at 900 °C” is not a sufficient process history.

Solid-phase crystallization is different from direct poly growth. Depositing an amorphous precursor and crystallizing it later can produce a different nucleation density, texture, roughness, defect population, and stress than direct LPCVD polysilicon. It is often useful when deposition coverage or temperature must be separated from crystallization. The added thermal step and volume/network rearrangement must be designed into the stack.

Laser or rapid thermal crystallization creates another microstructure class. Short thermal excursions can limit substrate heating or create large grains, but absorption, melt depth, overlap, edge effects, and pattern topography introduce spatial modes. This belongs to LTPS or recrystallization process ownership rather than being treated as a drop-in LPCVD replacement.

Surface roughness records nucleation and competitive growth. Protrusions can arise where locally favored nuclei grow faster; columnar grains and texture can amplify relief with thickness. Roughness may be harmful for a thin dielectric, lithography focus, contact, or pattern transfer, yet intentionally high area is valuable in specialized capacitor structures. The correct target comes from integration, not from “smoother is always better.”

AFM numbers need a measurement definition. RMS roughness depends on scan size, pixel density, filtering, tip shape, slope removal, and whether rare nodules are included. A small scan can miss particle-scale defects; a large optical map can miss nanoscale texture. Report the spatial bandwidth and pair AFM with haze, defect inspection, and microscopy.

Stress develops during island coalescence and grain evolution. Boundary formation, adatom incorporation, hydrogen, impurities, texture, and void elimination contribute intrinsic stress. Thermal-expansion mismatch between silicon film, substrate, and other layers adds stress during cooldown and later cycling. Anneal-driven grain growth can relax one component while adding another.

Average stress can hide a stress gradient. A film whose structure evolves from interface to surface can carry different stress through its thickness. That gradient curls released MEMS beams even when wafer-curvature average stress is near zero. Deposit partial thicknesses, use released test structures, and compare top/bottom process sequences when structural flatness matters.

Wafer curvature is useful but conditional. Stoney-type extraction assumes a film much thinner than the substrate, known substrate biaxial modulus, uniformity, and small deflection. Edge exclusion, backside deposition, pre-existing bow, and patterned coverage can bias the result. Measure the same wafer before and after deposition and after relevant thermal cycles.

Conformality follows surface kinetics and feature transport. LPCVD can coat sidewalls and recesses well when precursor reaches the entire feature and reaction probability is favorable. High sticking, depletion, or byproduct inhibition can reduce bottom coverage. Quote top/sidewall/bottom thickness at stated aspect ratio, pitch, and loading rather than applying a blanket “conformal” label.

Conformal growth can close a gap before filling it. Opposing sidewalls approach, and overhang or faster field growth can create a seam or void. Deposition–etch cycling, lower sticking chemistry, changed pressure, or a different fill architecture may be needed. Cross-section the most difficult patterned feature; a blanket monitor cannot reveal pinch-off.

Pattern loading can alter local growth. Dense topography changes exposed area, reactant consumption, conductance, radiation, and local thermal response. Wafer-scale thickness uniformity may coexist with pitch-dependent film thickness or microstructure. Include open and dense structures in qualification and measure both film geometry and properties.

Batch furnaces have axial signatures. Temperature zones, inlet depletion, exhaust conductance, boat spacing, dummy wafers, load size, tube coating, and wafer emissivity affect deposition along the boat. Center-slot data cannot qualify the load. Map rate, thickness, phase, stress, roughness, and sheet resistance at multiple slots and radial locations.

Temperature calibration must reach the wafer, not stop at the furnace controller. Thermocouple location, tube coating, wafer load, boat material, emissivity, ramp, and gas flow create offsets. A small real-temperature change near the phase-transition region can look like unexplained grain or roughness drift. Correlate calibrated thermal evidence with deposition-rate and phase monitors.

Chamber walls are a second substrate. They consume precursor, alter residence and radiation, build a stressed silicon coating, and eventually release flakes. Freshly cleaned, seasoned, and end-of-run states need not produce the same wafer film. Track deposited mass or integrated exposure, not wafer count alone, and define seasoning before product.

Polysilicon particle excursions have multiple diagnostic signatures. Gas-phase nucleation produces powder; stressed wall film sheds flakes; boat contact creates scratches or chips; contaminated surfaces seed nodules; downstream deposits can return through pressure events. Defect morphology, composition, location, and time-since-clean separate these mechanisms better than total particle count.

Cleaning changes the next process state. Chemical or plasma cleaning alters wall roughness, termination, emissivity, contamination, and conductance. Overclean can attack quartz or hardware; insufficient clean leaves a mechanically unstable coating. The first wafers after maintenance should verify rate, phase, particles, stress, and contamination before product qualification.

Native oxide at a contact interface is consequential. For a polysilicon-to-silicon contact, an interfacial oxide can raise resistance or block intended epitaxial registry. For deposition on an insulator, controlled oxide may be the intended isolation. Preclean chemistry, rinse/dry, queue time, ambient, and thermal desorption should match the interface function and contamination limits.

Oxygen and carbon can change crystallization and boundaries. Sources include precursor purity, leaks, wet surfaces, furnace memory, polymer residue, and substrate outgassing. SIMS, XPS, or calibrated bulk methods can identify contamination, while electrical, phase, and etch response reveal its consequences. A clean thickness map is not contamination evidence.

Hydrogen is both reaction product and material participant. Hydrogen termination affects adsorption and surface diffusion; incorporated hydrogen can passivate defects and later leave during anneal. Hydrogen partial pressure and pump behavior can therefore influence rate and structure. Treat carrier/dilution gas purity, exhaust conductance, and post-deposition thermal evolution as linked.

Oxidation consumes polysilicon and follows its microstructure. Grain boundaries and dopant can change local oxidation kinetics; the growing oxide redistributes stress and may smooth or reshape the surface. If polysilicon is later oxidized to form a dielectric or sacrificial consumption, qualify remaining silicon thickness, oxide uniformity, dopant redistribution, and interface roughness.

Silicidation depends on the starting poly film. Thickness, dopant, grain structure, native oxide, surface contamination, and roughness influence metal reaction, phase formation, agglomeration, and sheet resistance. A salicide result cannot be optimized independently of the deposited and annealed polysilicon beneath it.

Dry etch sees grains, boundaries, dopant, and mask topography. Chlorine- or bromine-based plasma response, sidewall roughness, notching, residue, and selectivity can shift with film structure and electrical charging. Etch qualification should use the actual poly thickness, dopant state, underlayer, hard mask, feature pitch, and post-deposition anneal.

Wet etch and release behavior are also microstructure-sensitive. Alkaline silicon etchants and mixed chemistries can attack orientations and grain boundaries differently, creating roughness or undercut variation. MEMS release selectivity and structural integrity require the exact production poly state, not a generic handbook rate.

Metrology should connect structure to function. Ellipsometry or reflectometry supplies thickness; cross-sectional SEM/TEM shows coverage and grains; AFM measures selected roughness bandwidth; XRD and Raman assess phase, texture, crystallite response, and stress with model limits; wafer curvature measures net stress; four-point probe maps sheet resistance; SIMS tracks dopant and impurities. No single method certifies “good poly.”

Phase labels require detection-limit discipline. Raman peak shape, XRD intensity, electron diffraction, and TEM sample volume answer different questions. A mostly amorphous film may contain sparse nuclei, while a thin poly film may generate weak XRD signal. State what volume, area, and minimum fraction each method can see.

Grain size is not one number. Plan-view and cross-sectional images sample lateral and vertical dimensions; XRD coherent-domain size is not automatically the visible grain size; texture biases diffraction; image thresholding changes the distribution. Report the method, distribution, film depth, thickness, and number of sampled fields.

Thickness control cannot compensate for structure drift. Extending time can restore target thickness after rate falls, but nucleation, grain structure, stress, roughness, contamination, and conformality may remain off. Deposition rate itself is a leading health signal. Any time correction should trigger correlated material checks.

Sheet resistance is powerful when interpreted with thickness. Rs can flag dopant activation, contamination, grain-boundary barriers, or thickness variation, but the same Rs can result from a thick resistive film or a thin conductive one. Use independently measured thickness and spatial maps; contactless methods and four-point probe have different edge and substrate assumptions.

A useful process window is multidimensional. Sweep actual temperature across kinetics and phase; pressure and silicon-source partial pressure across transport and powder risk; loading across depletion; thickness across texture and stress evolution; underlayer across incubation; dopant across growth response; and anneal across crystallization, activation, grain growth, and stress.

Factor interactions are the point of the experiment. Temperature sensitivity can change with pressure, loading, or wall state; doping response can change with phase; roughness can accelerate beyond a critical thickness. A designed experiment plus mechanistic plots is more transferable than one-factor tuning around a lucky recipe.

Chamber matching requires response surfaces, not copied set points. Match rate, axial/radial modes, phase, grain/texture, roughness, stress, particles, contamination, and electrical response across meaningful perturbations. Hardware geometry, thermal offsets, pump conductance, and wall age can make identical commands produce different films.

Production control needs leading and lagging indicators. Leading inputs include precursor delivery, pressure, temperature zones, pump/exhaust state, load configuration, maintenance and seasoning exposure. Lagging outputs include thickness/rate, phase proxy, Rs, stress, roughness samples, particle signatures, and periodic microscopy/composition. Multivariate trends reveal drift before a hard specification fails.

Safety starts with the real chemistry. Silane and related hydrides can be pyrophoric; hydrogen is flammable; dopant hydrides are acutely hazardous; chlorinated precursors and cleaning products may be toxic or corrosive. Gas cabinets, compatible delivery, detection, purge, ventilation, abatement, interlocks, maintenance controls, and current SDS/site procedures are mandatory. Process optimization never substitutes for an engineered hazard review.

Exhaust design must anticipate silicon-containing solids and changing conductance. Powder, wall flakes, pump deposits, and cleaning byproducts create restriction and maintenance exposure. Track foreline pressure and pump performance, control temperature and dilution where appropriate, and define safe cleaning and disposal for the actual precursor and dopant set.

Application pages should retain their specialized ownership. Gate poly owns gate-stack work function and depletion; resistor poly owns precision TCR and trimming; in-situ doping owns dopant chemistry; amorphous silicon owns the precursor amorphous state; LTPS owns display-scale crystallization; MEMS pages own released structures; backside-seal pages own backside gettering and sealing. This page owns how deposited polycrystalline silicon nucleates, grows, evolves, and is qualified across those uses.

A production-worthy polysilicon film is defined by its future, not its deposition endpoint. Thickness, phase, grain distribution, texture, boundary chemistry, roughness, stress and gradient, impurities, dopant activation, conformality, and particles must remain acceptable after implant, anneal, oxidation, etch, silicidation, release, and packaging. That is the material the device actually sees.

Temperature-phase window

In-situ doping versus activation

Final-state production release