Power analysis is the EDA discipline of estimating and optimizing how much electrical power a chip consumes under realistic workload conditions — predicting dynamic switching power, short-circuit power, and static leakage current across billions of transistors so designers can meet the thermal and battery-life budgets that determine whether a chip ships or fails qualification. At 3–5 nm nodes, power analysis is no longer a sign-off afterthought: it drives architecture decisions from day one because the power wall — not transistor density — is the binding constraint on performance.

The three components of chip power. Total power dissipation is the sum of three mechanisms, each with distinct physics and optimization levers:

$$P_{\text{total}} = P_{\text{dynamic}} + P_{\text{short-circuit}} + P_{\text{leakage}}$$

$$P_{\text{dynamic}} = \alpha \cdot C_{\text{load}} \cdot V_{\text{DD}}^2 \cdot f$$

$$P_{\text{leakage}} = V_{\text{DD}} \cdot I_{\text{leak}} = V_{\text{DD}} \cdot W \cdot I_0 \cdot e^{-V_t / (n \cdot V_T)}$$

where $\alpha$ is the switching activity factor (fraction of nodes toggling per clock cycle), $C_{\text{load}}$ is the total switched capacitance, $V_{\text{DD}}$ is supply voltage, $f$ is clock frequency, $I_0$ is the sub-threshold leakage prefactor, $V_t$ is threshold voltage, $n$ is the sub-threshold slope factor, and $V_T = kT/q$ is the thermal voltage. Dynamic power dominates in high-performance designs (GPUs at 1–2 GHz); leakage dominates in always-on IoT/mobile designs at low activity.

Why power analysis matters for AI chips. A modern AI accelerator at 5 nm dissipates 300–700 W in an 800 mm² die. That power creates heat (requiring expensive cooling), draws current (stressing the power delivery network), and costs electricity (the largest operating expense in AI datacenters). If power analysis underestimates the actual consumption, the chip may throttle, overheat, or fail reliability qualification. If it overestimates, designers waste area on unnecessary power mitigation — reducing the compute density that drives TOPS.

The power analysis flow — from RTL to sign-off:

Switching activity — the hardest input to get right. The accuracy of power analysis depends almost entirely on the quality of the switching-activity data. Two approaches:

• Vectored (simulation-based): Run RTL or gate-level simulation with realistic workload stimulus, capture toggle counts per net in VCD (Value Change Dump) or SAIF (Switching Activity Interchange Format). Most accurate, but slow (days for full-chip) and stimulus-dependent — if your benchmark doesn't exercise the worst case, the estimate is optimistic.
• Vectorless (statistical): Propagate estimated activity rates (e.g. 10–20% for data, 50–100% for clocks) from primary inputs through the logic cone. Fast (minutes), but less accurate and may miss workload-specific hotspots.

Best practice: vectorless for early estimation, vectored with representative workloads for sign-off.

Power optimization techniques — what the tools do:

• Multi-Vt assignment: Replace fast (LVT, high-leakage) cells with slower (HVT, low-leakage) cells on non-critical timing paths. Can reduce leakage by 40–60% with <1% performance loss.
• Clock gating: Insert ICG cells to shut off clock to idle flip-flops. Reduces clock-tree dynamic power by 40–70%.
• Operand isolation: Gate the inputs of combinational logic when its output is unused (prevents useless toggling).
• Power shut-off (PSO) / power gating: Cut VDD to entire blocks when idle using header/footer sleep transistors. Eliminates both dynamic and leakage, but requires retention flip-flops and isolation cells.
• Dynamic voltage and frequency scaling (DVFS): Scale VDD and frequency together at runtime based on workload demand. Power scales as $V^2 \cdot f$ — a 20% voltage reduction gives ~36% dynamic power savings.
• Body biasing: Forward body bias to speed critical paths (at cost of leakage), reverse body bias to reduce leakage in idle modes.

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<text x="480" y="28" fill="#e5e7eb" font-size="16" font-weight="700" text-anchor="middle">Power analysis flow — from architecture to sign-off</text>

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<text x="100" y="85" fill="#c9c3f2" font-size="11" text-anchor="middle" font-weight="600">Architecture</text>
<text x="100" y="100" fill="#8a8a86" font-size="9" text-anchor="middle">Power budget</text>
<text x="100" y="112" fill="#8a8a86" font-size="9" text-anchor="middle">±30–50%</text>

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<text x="270" y="85" fill="#bff0bf" font-size="11" text-anchor="middle" font-weight="600">RTL Estimation</text>
<text x="270" y="100" fill="#8a8a86" font-size="9" text-anchor="middle">VCD/SAIF activity</text>
<text x="270" y="112" fill="#8a8a86" font-size="9" text-anchor="middle">±15–25%</text>

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<text x="440" y="85" fill="#e8d44d" font-size="11" text-anchor="middle" font-weight="600">Synthesis Opt</text>
<text x="440" y="100" fill="#8a8a86" font-size="9" text-anchor="middle">Multi-Vt, clock gating</text>
<text x="440" y="112" fill="#8a8a86" font-size="9" text-anchor="middle">±10–20%</text>

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<text x="610" y="85" fill="#e0913a" font-size="11" text-anchor="middle" font-weight="600">Post-PnR</text>
<text x="610" y="100" fill="#8a8a86" font-size="9" text-anchor="middle">Real parasitics</text>
<text x="610" y="112" fill="#8a8a86" font-size="9" text-anchor="middle">±5–10%</text>

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<text x="780" y="85" fill="#dfafdf" font-size="11" text-anchor="middle" font-weight="600">Sign-off</text>
<text x="780" y="100" fill="#8a8a86" font-size="9" text-anchor="middle">All corners, vectored</text>
<text x="780" y="112" fill="#8a8a86" font-size="9" text-anchor="middle">±3–5%</text>

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<text x="480" y="155" fill="#e5e7eb" font-size="13" font-weight="600" text-anchor="middle">Typical 5nm GPU power breakdown</text>

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<text x="250" y="190" fill="#fff" font-size="10" text-anchor="middle">Dynamic switching 50%</text>
<text x="410" y="190" fill="#1a1a17" font-size="10" text-anchor="middle">Clock tree 30%</text>
<text x="510" y="190" fill="#fff" font-size="10" text-anchor="middle">Leakage 20%</text>

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<text x="480" y="235" fill="#e5e7eb" font-size="13" font-weight="600" text-anchor="middle">Power optimization techniques</text>

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<text x="135" y="275" fill="#8fe3bd" font-size="10" text-anchor="middle" font-weight="600">Clock Gating</text>
<text x="135" y="292" fill="#8a8a86" font-size="9" text-anchor="middle">−40–70% clock power</text>

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<text x="325" y="292" fill="#8a8a86" font-size="9" text-anchor="middle">−40–60% leakage</text>

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<text x="515" y="275" fill="#8fe3bd" font-size="10" text-anchor="middle" font-weight="600">Power Gating (PSO)</text>
<text x="515" y="292" fill="#8a8a86" font-size="9" text-anchor="middle">−95% idle block power</text>

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<text x="705" y="292" fill="#8a8a86" font-size="9" text-anchor="middle">−36% at −20% voltage</text>

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<text x="480" y="340" fill="#8a8a86" font-size="10" text-anchor="middle">Power = activity × capacitance × V² × freq — every optimization attacks one of these terms</text>
<text x="480" y="358" fill="#6f6f6a" font-size="9" text-anchor="middle">CFS Thermal Simulator (/thermal) models the junction temperature that power creates</text>

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IR-drop and power integrity — the voltage delivery problem. Power analysis doesn't stop at estimating total watts — it must also verify that every transistor receives adequate voltage. Current flowing through the resistive power grid creates IR-drop (voltage loss), and rapid current transients (di/dt from clock edges) cause Ldi/dt voltage noise. If local VDD sags below the minimum operating voltage, timing violations occur. Power-integrity sign-off (Voltus, RedHawk) combines the switching-current waveform from power analysis with the extracted power-grid resistance/inductance to map worst-case voltage droop across the die. The CFS Power Delivery keyword and the Thermal Simulator at /thermal model the downstream effects.

Power analysis for AI accelerators — unique challenges. AI chips have extreme power characteristics: (1) very high peak power during dense matmul bursts (all tensor cores active), (2) rapid power cycling between compute-bound and memory-bound phases (50% power swing in microseconds), (3) large on-die SRAM arrays with significant leakage, and (4) HBM PHY I/O power that scales with bandwidth utilization. Power analysis must capture these workload-dependent transients — a single "average power" number is insufficient for thermal design or PDN sign-off.