Power consumption is the rate at which a chip, board, rack, or facility draws electrical energy, measured in watts. Power sets performance, cooling, packaging, reliability, rack density, electricity cost, and deployment capacity for AI systems. Dynamic CMOS power scales approximately with switching activity, capacitance, frequency, and voltage squared; static power arises from leakage and grows with device count, process, voltage, and temperature. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. A claim states boundary, input versus delivered DC power, workload, utilization, clocks, voltage, temperature, measurement interval, auxiliaries, and whether it is instantaneous, average, capped, or design power.

Architecture, quantitative model, and operating behavior. Chip power includes compute, SRAM/cache, NoC, memory PHY, SerDes, clocking, control, and leakage. Board power adds HBM, regulators, fans and links; rack power adds CPUs, NICs, switches and cooling distribution; facility power adds conversion and heat rejection. DVFS trades voltage and frequency, clock or power gating disables idle regions, workload schedulers manage caps, and boost uses thermal/electrical headroom. TDP is a thermal design target or product policy, not a universal measurement of actual draw. Active, idle, leakage, dynamic, transient, average, peak, TDP/TBP, board, rack, IT, and facility power serve different engineering decisions. Modern accelerator boards occupy several-hundred-watt classes and dense racks can reach tens of kilowatts. Useful analysis separates arithmetic, memory hierarchy, interconnect, storage, control, and queuing. It counts operations and bytes at each boundary, identifies dependencies and reuse, estimates ideal ceilings, and then uses counters and traces to explain the gap between the model and measurement. Ratios without a clearly named numerator and denominator invite invalid comparisons. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints.

Implementation, hardware mapping, and bottlenecks. Reduce switching, voltage, unnecessary precision and data movement; gate idle blocks; optimize memory and communication; cap power; balance phases; provision regulator transient response; instrument rails; and co-design cold plates or airflow. Grid, switchgear, UPS, PSU, busbar, board VRMs, package delivery, and on-die networks incur losses and droop. Hotspots, current density, connector limits, and thermal resistance can throttle before average power limits. Equating TDP with actual power, measuring only the GPU while excluding memory or host, ignoring transients and conversion loss, extrapolating idle averages, or optimizing chip power while increasing runtime can worsen total energy. Begin with a correct reference and representative shapes. Profile end to end, classify the dominant resource, inspect kernel and system timelines, change one bottleneck at a time, and remeasure because optimization moves pressure elsewhere. Tiling, fusion, batching, vectorization, layout, precision, compression, overlap, prefetch, sharding, and algorithm choice are useful only when they reduce the limiting resource. The execution path spans registers, local SRAM and caches, HBM or GDDR, host DRAM, PCIe or coherent links, scale-up fabric, network, and storage. Compute units consume tensors only when compilers and kernels issue enough independent work and the hierarchy supplies operands. Package wiring, memory stacks, clocks, voltage, thermal headroom, and power delivery determine sustained limits. Frequent mistakes include quoting peak instead of achieved rates, omitting data conversion and transfer, measuring a cached toy input, timing asynchronous work without synchronization, mixing decimal and binary units, ignoring warmup or throttling, changing precision or quality, averaging away tails, and optimizing a component that is not on the critical path.

Measurement, validation, and engineering controls. Measure rail and wall power with calibrated instruments, synchronize workload phases, sample transients, sweep caps and thermals, verify throttling, compare telemetry to external meters, and run sustained workloads. Watts by rail/component, voltage, current, transient slew, utilization, temperature, clock, leakage, conversion efficiency, PUE, energy per task, performance per watt, and cost matter. Correlate time-aligned power, clock, temperature, utilization, memory, and workload traces; component isolation and cap sweeps reveal where watts produce useful work. Verification combines analytical bounds, microbenchmarks, hardware counters, kernel timelines, end-to-end traces, scaling sweeps, sensitivity to batch and shape, cold and warm runs, long-duration thermal tests, correctness comparisons, fault and congestion tests, and independent reproduction. Roofline and queueing models guide diagnosis but must be calibrated against the deployed machine. Benchmark code, datasets, model and compiler artifacts, drivers, firmware, topology, clock and power settings, environment, commands, raw samples, counter traces, and analysis notebooks remain versioned. Continuous tests detect regressions in quality, latency, throughput, bandwidth, memory, power, and cost, with thresholds chosen from variance rather than a single run. Published comparisons disclose configuration, exclusions, tuning effort, measurement boundary, quality criteria, and uncertainty. Energy and carbon claims distinguish chip, IT, and facility boundaries and avoid extrapolating one benchmark to all workloads. Owners review regressions and retain evidence sufficient to reproduce decisions.

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Selection and system-level application. Choose power envelopes from workload throughput, thermal system, rack density, electrical capacity, reliability, and energy cost, then optimize useful work within that envelope. AI accelerators, CPUs, mobile SoCs, datacenters, edge inference, HPC, networking, storage, and semiconductor fabs all budget power. Power consumption links transistor switching, architecture, compiler activity, workload, package delivery, board design, cooling, facility infrastructure, and operations. Optimization is a system exercise across algorithms, precision, kernels, compiler, runtime, accelerator, memory, interconnect, scheduler, serving policy, cooling, and facility limits. Removing one ceiling often exposes another, so architecture decisions should optimize time and energy to a useful result rather than an isolated metric. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.