Power Delivery 3D Integration

# Power Delivery in 3D Integration: Architectures, Target Impedance & BSPDN

In high-performance computing (HPC) and artificial intelligence (AI) silicon systems, Power Delivery in 3D Integration represents the architectural, physical, and electrical engineering discipline required to deliver hundreds to thousands of amperes of clean, stable current to multi-die vertical stacks. As advanced compute nodes operate at sub-$0.75\,\text{V}$ supply voltages ($V_{DD}$) while drawing total core currents exceeding $1000\text{ to }1500\,\text{A}$, power distribution networks (PDNs) face unprecedented challenges in mitigating static resistive $IR$ drop and dynamic inductive $L \cdot di/dt$ voltage droop.

In conventional 2D chips and early 2.5D packages, power must travel through the entire frontside back-end-of-line (BEOL) interconnect stack (15 to 20 metal layers), consuming over $30\%$ of valuable metal routing resources and incurring severe resistive losses. In true 3D heterogeneous systems, vertical power delivery leverages Through-Silicon Vias (TSVs), fine-pitch hybrid bonding pads, Deep Trench Capacitors (DTCs), and revolutionary Backside Power Delivery Networks (BSPDN)—such as Intel PowerVia and TSMC SuperPower. By decoupling the power grid from signal routing and delivering power directly to transistor terminals from the rear of the wafer, BSPDN reduces $IR$ drop by more than $85\%$ and eliminates power-induced electromigration bottlenecks.

Frontside vs. Backside Power Delivery (BSPDN) Architecture eliminating BEOL power congestion, resistive IR drop, and parasitic loop inductance 1. CONVENTIONAL FRONTSIDE (FSPDN) VDD VSS Congested BEOL Stack (M15 to M1) Signals Compete with Power Grid (> 35% Area Loss) FinFET / GAA FinFET / GAA Bulk Silicon Substrate (775 μm, Passive) FSPDN Limitations at < 2nm Nodes: • Severe IR Drop: ΔV_IR > 100–140 mV (> 15% of nominal VDD) • Narrow M1/M0 copper vias exhibit high electromigration risk • BEOL wiring tracks blocked by power rails, degrading RC delays 2. BACKSIDE POWER DELIVERY (BSPDN / POWERVIA) Frontside BEOL: 100% Dedicated Signal Wiring Zero Power Grid Congestion | Relaxed Wire Pitch BPR VDD BPR VSS GAA Nanosheet Logic Thinned Silicon Substrate (t ≈ 100–300 nm) nTSV nTSV Backside VDD Backside VSS Thick Cu Mesh BSPDN Breakthrough Metrics: • > 85% Reduction in IR Drop: ΔV_IR drops to < 20 mV • Buried Power Rails (Ru / W / Cu) placed below active fin • Nano-TSVs (aspect ratio 3:1, diameter 50–100 nm) link directly • 15–25% Standard Cell Area Scaling (track height reduction) • Unlocks pure signal optimization in frontside BEOL • Commercial adoption: Intel 20A/18A PowerVia, TSMC A16 SuperPower

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## 1. PDN Target Impedance Formulation & High-Frequency Noise Physics

To ensure operational stability, the power distribution network impedance $Z_{PDN}(f)$ seen by the active switching transistors must remain below an engineered target impedance ($Z_{target}$) across the entire operating frequency spectrum (DC to multi-GHz).

PDN Target Impedance Profile & Multi-Tier Decoupling frequency-domain impedance suppression across VRM, package MLCC, deep trench, and on-die MIM decaps PDN IMPEDANCE vs. FREQUENCY Z(f) 10 mΩ 1 mΩ 100 μΩ 10 μΩ 1 μΩ PDN Impedance |Z| → 10 kHz 1 MHz 50 MHz 500 MHz 5 GHz Frequency (f) → Z_target = 75 μΩ VRM Reg Package MLCC DTC Bridge On-Die MIM 3D VERTICAL DECOUPLING HIERARCHY Top Compute Core Die (0.75V, 1000A) MIM (40 fF/μm²) MIM (40 fF/μm²) Direct Cu-Cu Hybrid Bonding (Pitch < 2 μm) Base Die / Active Interposer with DTCs DTC Array: > 400 nF/mm² Sub-5 pH Inductance Multi-Layer Organic Package Substrate Surface-Mounted Land-Side MLCCs (0.1–10 μF) Hierarchy Bandwidth & ESL Responsibilities: • On-Die MIM (f > 500 MHz): Zero lead ESL; dampens di/dt edges • Deep Trench DTC (20–200 MHz): Suppresses mid-frequency bounce • Package MLCC (100 kHz–10 MHz): Supplies multi-cycle burst energy • Voltage Regulator Module (DC–100 kHz): Fast multi-phase loop regulation

### 1.1 Mathematical Formulation of Target Impedance
The target impedance $Z_{target}$ is the maximum permissible PDN impedance that restricts transient supply voltage fluctuations within the allowed ripple tolerance ($\Delta V_{ripple}$):

$$Z_{target} = \frac{V_{DD} \cdot \Delta V_{ripple}}{\Delta I_{transient}}$$

Where:
- $V_{DD}$ is the nominal core supply voltage (e.g., $0.75\,\text{V}$).
- $\Delta V_{ripple}$ is the allowable percentage ripple (typically $\pm 5\%$, corresponding to $37.5\,\text{mV}$).
- $\Delta I_{transient}$ is the instantaneous step current demand caused by clock-gating wake-up or parallel matrix-multiplication execution (typically $50\%$ of peak load, or $500\,\text{A}$ for a $1000\,\text{A}$ processor).

For these representative parameters:

$$Z_{target} = \frac{0.75\,\text{V} \cdot 0.05}{500\,\text{A}} = \frac{0.0375\,\text{V}}{500\,\text{A}} = 75\,\mu\Omega$$

Maintaining an impedance of $\le 75\,\mu\Omega$ across multiple frequency decades requires precise damping of the LC anti-resonance peaks formed between adjacent decoupling capacitor tiers.

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## 2. Dynamic Voltage Droop Mechanics ($L \cdot di/dt$)

The total time-domain voltage deviation $\Delta V_{total}(t)$ observed at the transistor terminals during transient switching consists of resistive and inductive contributions:

$$\Delta V_{total}(t) = I(t) \cdot R_{PDN} + L_{loop} \cdot \frac{dI(t)}{dt} - \frac{1}{C_{eff}} \int_0^t [I(\tau) - I_{VRM}(\tau)] \, d\tau$$

Where:
- $R_{PDN}$ is the total lumped resistance from the power source to the active cell.
- $L_{loop}$ is the effective parasitic loop inductance of the vertical interconnect path.
- $dI/dt$ is the current slew rate during clock-edge transitions (exceeding $1000\text{ to }3000\,\text{A/ns}$ in modern GPU/NPU compute clusters).

### 2.1 First-Droop vs. Second-Droop Dynamics
1. First Droop ($t < 1\text{ to }2\,\text{ns}$):
- Driven entirely by high-frequency on-die switching and package/die loop inductance ($L_{die} \cdot di/dt$).
- Can only be suppressed by low-inductance on-die MIM capacitance and deep trench capacitors situated in extreme proximity ($< 10\,\mu\text{m}$) to the switching gates.
2. Second Droop ($t \approx 10\text{ to }50\,\text{ns}$):
- Driven by the anti-resonance between package parasitic inductance ($L_{pkg}$) and total die capacitance ($C_{die}$):

$$f_{anti} = \frac{1}{2\pi \sqrt{L_{pkg} C_{die}}}$$
  • Suppressed by integrating high-capacitance Deep Trench Capacitors (DTC) with sub-10 pH equivalent series inductance (ESL) into active interposers or base dies.

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## 3. Backside Power Delivery Network (BSPDN) Physics

Backside Power Delivery Networks represent the most fundamental transformation in semiconductor metallization since the introduction of dual-damascene copper.

### 3.1 Structural Components of BSPDN
1. Buried Power Rails (BPR):
- Ultra-low-resistance refractory metal rails (ruthenium, tungsten, or cobalt) buried within dielectric trenches beneath the active transistor fins/nanosheets.
- Cross-sectional dimensions: width $\approx 20\text{ to }30\,\text{nm}$, depth $\approx 60\text{ to }100\,\text{nm}$.
2. Nano-Through-Silicon Vias (nTSVs):
- Extremely high-density, low-aspect-ratio vertical vias fabricated through extremely thinned silicon ($t_{Si} \approx 100\text{ to }300\,\text{nm}$).
- Diameter: $50\text{ to }100\,\text{nm}$; height: $150\text{ to }300\,\text{nm}$ (aspect ratio $< 3:1$).
- Resistance per nTSV: $R_{nTSV} \approx 0.2\text{ to }0.5\,\Omega$. With millions placed across the die, area-normalized conductance approaches ideal sheet levels.
3. Backside Thick Metallization Grid (B1–B4):
- Wide, thick copper buses (thickness $0.5\text{ to }2.0\,\mu\text{m}$) patterned on the polished rear face of the wafer.
- Bypasses the 15-20 thin, high-resistance layers of the frontside BEOL entirely.

+----------------------------------------------------------------------------------------------------+
|                               FSPDN vs. BSPDN COMPARATIVE BENCHMARK                                |
+-----------------------+--------------------+-------------------+-----------------------------------+
| PERFORMANCE METRIC    | FRONTSIDE (FSPDN)  | BACKSIDE (BSPDN)  | PHYSICAL MECHANISM                |
+-----------------------+--------------------+-------------------+-----------------------------------+
| Static IR Drop        | 100 to 140 mV      | 15 to 25 mV       | Bypasses 15+ thin BEOL layers;    |
| (at 1000A peak)       | (> 15% VDD loss)   | (< 3% VDD loss)   | delivers power directly via nTSVs.|
+-----------------------+--------------------+-------------------+-----------------------------------+
| BEOL Signal Routing   | 65% to 70% of tracks| 100% of tracks    | Power grids eliminated from       |
| Availability          | available          | dedicated to sig  | frontside metallization stack.    |
+-----------------------+--------------------+-------------------+-----------------------------------+
| Standard Cell Area    | Baseline (1.0×)    | 0.75× to 0.85×    | BPR allows standard cell track    |
| Scaling               |                    | (15-25% shrink)   | height to drop from 6T/5T to 4T.  |
+-----------------------+--------------------+-------------------+-----------------------------------+
| Maximum Operating     | Baseline           | +6% to +10% F_max | Reduced IR drop preserves full    |
| Clock Frequency       |                    | at iso-voltage    | overdrive voltage (VGS - Vth).    |
+-----------------------+--------------------+-------------------+-----------------------------------+
| Electromigration Risk | High in narrow M1  | Negligible        | Thick backside copper carries bulk|
|                       | copper vias        |                   | current at low current density.   |
+-----------------------+--------------------+-------------------+-----------------------------------+

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## 4. Deep Trench Capacitor (DTC) Technology in 3D Stacks

To suppress dynamic voltage droop in 3D multi-die stacks, planar MOS or metal-insulator-metal (MIM) capacitors ($10\text{ to }40\,\text{fF/\mu m}^2$) are insufficient due to silicon area constraints.

### 4.1 3D Trench Aspect Ratio Scaling
Deep Trench Capacitors (DTCs) etch microscopic high-aspect-ratio holes or trenches ($30:1\text{ to }50:1$) into silicon using deep reactive-ion etching (DRIE). Atomic layer deposition (ALD) subsequently lines the trench surfaces with ultra-thin high-$\kappa$ dielectric nanolaminates (such as $\text{ZrO}_2\text{--Al}_2\text{O}_3\text{--ZrO}_2$ or $\text{HfO}_2$, $\kappa \approx 25\text{ to }40$) and metallic TiN/Ru electrodes.

The capacitance density $C_{DTC} / A_{footprint}$ scales with geometric trench surface enlargement:

$$\frac{C_{DTC}}{A_{footprint}} = \frac{\kappa \epsilon_0}{t_{ox}} \cdot \left[ 1 + \frac{2 \pi r \cdot d}{p^2} \right]$$

Where $r$ is trench radius, $d$ is etch depth ($5\text{ to }10\,\mu\text{m}$), $p$ is pitch, and $t_{ox}$ is effective oxide thickness (EOT $< 1.0\,\text{nm}$).
- Modern DTCs achieve capacitance densities exceeding $300\text{ to }500\,\text{nF/mm}^2$—more than $10\times$ higher than planar MIM capacitors.
- The vertical coaxial current geometry restricts equivalent series inductance (ESL) to $< 5\text{ to }10\,\text{pH}$, delivering unprecedented transient current injection within sub-nanosecond switching intervals.

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