Power Delivery Network (PDN) is the complete electrical path from the voltage regulator module (VRM) on the motherboard through the package to the on-die power grid — designed to maintain stable supply voltage (Vdd) within tight ripple margins (< 5% of nominal) despite fast transient current demands of billions of switching transistors.
PDN Components (Source to Sink)
1. VRM (Voltage Regulator Module): DC-DC converter on motherboard. Output impedance matters at < 100 KHz. 2. Bulk Capacitors: Large electrolytic/ceramic caps near VRM. Effective 10 KHz - 1 MHz. 3. Package Decoupling Caps: Surface-mount caps on package substrate. Effective 1 - 100 MHz. 4. On-Die Decoupling: MOS capacitance + dedicated decap cells. Effective 100 MHz - 10 GHz. 5. On-Die Power Grid: Metal mesh (M_top layers for Vdd/Vss) distributing current to every standard cell.
PDN Impedance Target
- Target impedance: $Z_{target} = \frac{V_{dd} \times ripple\%}{I_{max}}$
- Example: 0.75V supply, 3% ripple, 100A max current → $Z_{target}$ = 0.225 mΩ.
- This impedance must be maintained from DC to several GHz — requires decoupling at every frequency.
On-Die Power Grid Design
- Power mesh: Top 2-4 metal layers dedicated to Vdd and Vss stripes.
- Typical: M10/M12 horizontal stripes (5-10 μm pitch), M11 vertical stripes.
- Standard cell Vdd/Vss rail: M1 horizontal rails at top/bottom of cell row.
- Via stacks: Dense via arrays connect top metal mesh to M1 cell rails.
- IR drop: $\Delta V = I \times R_{grid}$ — current flowing through resistive metal grid causes voltage droop.
- IR drop target: < 3-5% of Vdd at maximum current.
PDN Analysis
| Analysis | What It Checks | Tool |
|---|---|---|
| Static IR Drop | DC voltage droop from current flow | RedHawk (Ansys), Voltus (Cadence) |
| Dynamic IR Drop | Transient voltage droop from switching | RedHawk-SC, Voltus |
| EM (Electromigration) | Current density vs. wire lifetime | Same tools |
| Impedance (Z) | Frequency-domain PDN response | HSPICE, PowerSI |
Decap Cells
- Dedicated standard cells containing only MOS capacitors between Vdd and Vss.
- Inserted in empty spaces during placement — provide on-die charge reservoir.
- Total on-die decap: 100-500 nF for a modern SoC.
The power delivery network is the circulatory system of a chip — designing it to deliver clean, stable voltage under extreme transient conditions determines whether a processor can sustain its peak frequency or must throttle due to voltage droop.
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