Power Grid Design and IR-Drop Analysis is the physical design discipline that creates the on-chip metal network distributing VDD and VSS to every standard cell, memory macro, and I/O — ensuring that voltage drop (IR-drop) across the resistive grid remains within the design margin (typically <5-10% of VDD) under worst-case switching activity, while meeting electromigration lifetime requirements at every wire segment and via.
Why IR-Drop Matters
Transistor drive current is proportional to (VDD - Vth)². A 5% drop in VDD reduces drive current by ~10%, slowing the circuit and potentially causing timing violations. At a 0.75V supply (common at 5nm), a 5% IR-drop is only 37.5 mV — comparable to the Vth variation budget. Excessive IR-drop in the clock network causes clock jitter and skew, further degrading timing margins.
Power Grid Architecture
- Top Metal (Global Grid): Wide metal stripes on the uppermost metal layers (M10-M16) form a coarse grid that distributes power from the C4 bump connections across the die. Wire widths: 1-10 um. The grid pitch and width are determined by the total current demand per unit area.
- Intermediate Metal: Medium-pitch power stripes on M5-M9 refine the power distribution, feeding current from the global grid toward the standard cells below.
- Standard Cell Rails: M1/M0 power rails run along each standard cell row, directly connecting to the VDD and VSS pins of every cell. The most heavily loaded rails — each segment carries current for the cells in its row.
- Vias: Vertical connections between metal layers. Via arrays at grid intersections must handle the current flowing between levels. Total via resistance is often the dominant contributor to IR-drop.
IR-Drop Analysis
- Static IR-Drop: Assumes all cells draw their average current simultaneously. Solves the resistive network (Kirchhoff's equations) to find the steady-state voltage at every node. Simple but conservative.
- Dynamic IR-Drop: Simulates transient voltage droop when a large number of cells switch simultaneously (e.g., clock edge arrival). Uses time-domain simulation with switching activity data from gate-level simulation. Dynamic IR-drop can be 3-5x worse than static because simultaneous switching creates current surges (dI/dt) that the on-chip decoupling capacitance cannot fully absorb.
Decoupling Capacitors (Decaps)
Decap cells (standard cells containing only NMOS/PMOS capacitors between VDD and VSS) are inserted in empty spaces throughout the design. They act as local charge reservoirs, supplying instantaneous current during switching events and reducing dynamic IR-drop and power supply noise.
Electromigration (EM) Verification
Every power grid wire and via must carry its current load without exceeding the EM current density limit (jmax, determined by Black's equation for the target lifetime). EM violations require widening wires, adding parallel stripes, or increasing via count.
Power Grid Design is the arterial system of the chip — delivering electrical energy from the package bumps to every transistor with less than a few percent voltage loss, even when billions of gates switch simultaneously.