A power domain is a logically defined region of the chip where all cells share the same primary power supply and can be collectively managed — powered on, powered off, or operated at a specific voltage level — as a single unit in the chip's power architecture.

Power Domain Fundamentals

• Every cell on the chip belongs to exactly one power domain.
• All cells in a domain share the same VDD supply rail — they are powered up or down together.
• Different domains can operate at different voltages and can be independently power-gated.
• The boundaries between power domains are where special cells (isolation cells, level shifters) are required.

Why Power Domains?

• Power Gating: Entire blocks can be shut down during idle periods. Each independently switchable block is its own power domain.
• Multi-VDD: Different blocks can run at different voltages for power-performance optimization. Each voltage level defines a separate domain.
• Always-On Requirements: Control logic, wake-up circuits, and retention infrastructure must stay powered — they form a separate always-on domain.

Power Domain Components

• Supply Network: VDD and VSS rails for the domain — may be real (always-on) or virtual (switchable through power switches).
• Power Switches: Header or footer switches that connect/disconnect the domain from its supply. Only present for switchable domains.
• Isolation Cells: At every output crossing from a switchable domain to a powered-on domain — clamp outputs to safe values during power-off.
• Level Shifters: At every crossing between domains operating at different voltages — convert signal levels.
• Retention Cells: Flip-flops within switchable domains that need to preserve state across power cycles.

Power Domain Hierarchy

• A typical SoC might have:
• Always-On Domain: PMU, wake-up controller, RTC.
• CPU Domain: Processor core — power-gated during idle, DVFS for performance scaling.
• GPU Domain: Graphics — aggressively power-gated when not rendering.
• Peripheral Domains: UART, SPI, I2C — individually gated based on usage.
• Memory Domain: SRAM arrays — may use retention voltage (low VDD to maintain data without logic operation).
• I/O Domain: I/O pads — operates at interface voltage (1.8V, 3.3V).

Power Domain in UPF

create_power_domain CPU -elements {cpu_core}
create_power_domain GPU -elements {gpu_top}
create_power_domain AON -elements {pmu rtc wakeup}

Physical Implementation

• Power domains correspond to physical regions on the die with separate power grids.
• Domain boundaries must be cleanly defined — no cell can straddle two domains.
• Power grid routing for multiple domains is one of the most complex aspects of physical design.

Power domains are the fundamental organizational unit of low-power design — they define the granularity at which power can be managed, directly determining how effectively the chip can reduce power consumption during varying workloads.