Power Gating and State Retention is a low-power design technique that selectively disables power supply to unused logic domains while preserving critical state information, achieving 10-100x leakage reduction but introducing power management and wake-up latency challenges.

Power Domain Partitioning

• Domain Definition: Logically group functional units into independent power domains. Example: CPU power domain, GPU domain, memory domain, always-on (AO) domain (clock, power management).
• Island Domains: Smaller domains (module-level) enable fine-grain control but increase complexity. Coarser domains (cluster-level) simplify management but less power savings.
• Always-On Logic: Processor control, power manager FSM, interrupt handling remain powered. Consumes standby power but enables wake-up signaling.

Sleep Transistor and Header/Footer Configuration

• Header Transistor: High-Vth PMOS/NMOS between power supply and domain VDD. Controls power rail voltage; off-state disconnects VDD.
• Footer Transistor: High-Vth PMOS/NMOS between domain GND and VSS. Controls ground connection; off-state isolates from ground.
• Sizing: Over-sized transistors reduce on-state IR drop and wake-up time but increase area and leakage. Typically 2-5x larger than logic it drives.
• Multiple Transistor Stages: Stacked headers/footers reduce inrush current (dI/dt) during turn-on, preventing supply voltage droop and electromagnetic interference.

Isolation Cell and State Retention Flip-Flops (SRPG)

• Isolation Cells: Latches/gates on power-gated domain outputs prevent undefined states when domain unpowered. Forced to safe values (0 or 1) during power-down.
• Combinational Isolation: AND/NAND gate blocks output with static control signal. Propagates safe value to always-on domains.
• Sequential Isolation: Flip-flop holds output value during power transition. Enables fine-grain control of signal propagation timing.
• State-Retention Flip-Flop (SRPG): Specialized flip-flop with dual-rail latch (one in powered domain, one in always-on). Before power-down, state latched into always-on side.

Isolation Cell Implementation Details

• Timing Closure: Isolation latching must complete before power-gated domain powers down. Setup/hold constraints on isolation enable signal relative to clock.
• Data Validity: Isolation cells inserted on all state-holding elements (flip-flops, latches, memories). Non-state outputs safe-forced to 0 via gate logic.
• Always-On Power Consumption: Isolation latches and isolation logic themselves consume always-on power. Overhead: ~5-10% of gated logic power even when gated.

Power Manager FSM and Wake-Up Latency

• Power Manager Control: FSM coordinates power domain state transitions. Sequences: compute → idle → sleep → wakeup. Prevents races and maintains system consistency.
• Wake-Up Latency: Delay from wake-up request to domain functionality resuming. Dominated by header/footer turn-on (500ns-10µs typical). Clock restoration, isolation release add cycles.
• Retention Wake-Up: Gated domain powers on quickly (ms range) with state intact. Bypasses reset/initialization, but still requires PLL lock time, PMU settling.

Leakage Savings and Tradeoffs

• Leakage Reduction: Sub-threshold leakage scaling exponentially with supply voltage. Power-gating reduces leakage ~1000x vs normal standby (relies on high Vth sleep transistor).
• Area Overhead: Isolation cells, state-retention logic, power manager add ~10-20% area. Sleep transistor sizing substantial but benefits amortized across large domains.
• Timing Penalty: Wake-up latency adds to response time. Critical for real-time systems. Retention reduces latency vs full reset-required approaches.
• Application Examples: Mobile SoCs (CPU clusters gated during screen-off), server CPUs (core gating for power efficiency), audio codecs, wireless modems all use power gating.