Power grid design is the engineering of the on-chip power distribution network (PDN) that delivers supply voltage (VDD) and ground (VSS) to every transistor on the chip — ensuring reliable voltage delivery with minimal IR drop, electromigration risk, and area overhead.

Power Grid Architecture

• Global Power Grid: Top metal layers (thick, low-resistance metals) carry power across the chip from package bumps/pads to major blocks. Typically a mesh (orthogonal stripes on alternating layers) for redundancy and uniform distribution.
• Intermediate Distribution: Middle metal layers connect the global grid to local power rails. Transition from wide stripes to narrower wires.
• Local Power Rails: Lower metal layers deliver power directly to standard cells. In standard cell design, VDD and VSS rails run horizontally at the top and bottom of each cell row.
• Via Stacks: Vertical connections between metal layers — critical for carrying current between grid levels.

Design Considerations

• IR Drop Budget: Typically 5–10% of VDD is the maximum acceptable IR drop. At 0.7V VDD, that is only 35–70mV — requires careful grid design.
• Electromigration: Power grid wires carry DC current continuously — must meet EM current density limits. Key EM constraint in modern designs.
• Area Overhead: Power grid metal consumes routing resources. Typical overhead: 15–30% of metal area on lower layers, 30–50%+ on upper layers.
• Decoupling Capacitance: Place on-die decaps (MOS capacitors or MIM caps) to supply charge during dynamic current transients and reduce dynamic IR drop.

Power Bump/Pad Strategy

• Flip-Chip (C4/Micro-Bumps): Bumps distributed across the die area — power bumps are placed strategically near high-power blocks. Provides excellent power delivery.
• Wire-Bond: Power pads limited to the die periphery — longer current paths, higher IR drop. Requires wider power buses.
• Bump Ratio: Typically 30–50% of total bumps are dedicated to power/ground.

Multi-Voltage Design

• Modern SoCs use multiple voltage domains (high-performance cores at higher VDD, low-power blocks at lower VDD, I/O at yet another voltage).
• Each voltage domain needs its own power grid — with level shifters at domain boundaries and isolation cells for power gating.
• Power gating: Switches (header/footer transistors) disconnect idle blocks from VDD to eliminate leakage — the power grid must support the switch network.

Design Flow

1. Floor Planning: Allocate power bump locations and plan global power stripe widths. 2. Grid Generation: Automated tools create the mesh structure based on design rules and current estimates. 3. IR Drop Analysis: Verify voltage delivery across the die. 4. EM Analysis: Verify all segments meet current density limits. 5. Iterate: Add metal, bumps, or decaps to fix violations.

Power grid design is one of the most critical aspects of physical design — inadequate power delivery directly causes timing failures, yield loss, and reliability issues.