Power Grid Design is the process of creating a robust power distribution network (PDN) that delivers stable supply voltage from package pins to every transistor on the chip with minimal voltage drop and noise — requiring careful sizing of power straps, mesh layers, and decoupling capacitors to ensure that IR drop and L·di/dt noise remain within specified budgets across all operating conditions.

PDN Architecture:

• Hierarchical Distribution: power flows from package bumps → C4 bumps/bond pads → top-level power rings → power mesh (multiple metal layers) → power rails (M1/M2) → standard cell power pins; each level must handle progressively higher current density with lower resistance
• Power Mesh Topology: orthogonal metal straps on alternating layers (M5 horizontal, M6 vertical, M7 horizontal, etc.) form a grid; via stacks connect layers to create low-resistance vertical paths; mesh pitch (spacing between straps) typically 10-50μm depending on current density and metal layer
• Power Ring: thick metal ring around block or chip periphery collects current from I/O pads and distributes to internal mesh; ring width sized for worst-case current with margin for electromigration; typically uses top two metal layers (M8/M9 at 7nm) for lowest resistance
• Power Rail: M1 horizontal rails in standard cell rows provide VDD and VSS to cell power pins; rail width determined by cell height and current density; advanced nodes use buried power rails (backside power delivery) to free M1 for signal routing

IR Drop Analysis:

• Static IR Drop: DC voltage drop due to resistive losses in the power grid under steady-state current; calculated using DC analysis with average current consumption per instance; target static IR drop is typically 5-10% of nominal VDD (50-80mV at 1.0V supply)
• Dynamic IR Drop: transient voltage drop caused by simultaneous switching of many gates (L·di/dt effect); inductive component dominates at package level while resistive dominates on-chip; dynamic IR drop can reach 10-15% of VDD during worst-case switching events
• Vectorless Analysis: estimates worst-case IR drop without specific activity vectors by assuming maximum current draw in local regions; conservative but fast; used for early floorplanning and grid sizing decisions
• Vector-Based Analysis: uses gate-level simulation vectors to capture realistic switching activity; more accurate but requires representative test patterns; Cadence Voltus and Synopsys RedHawk perform vector-based dynamic IR drop analysis with full RLC extraction

Grid Sizing and Optimization:

• Current Density Limits: metal layers have maximum allowed current density (typically 0.5-2.0 mA/μm width) to prevent electromigration failures; power straps must be wide enough to handle peak current with margin; EM rules are more stringent for DC current (clock, power) than AC signal nets
• Resistance Calculation: sheet resistance (Ω/square) multiplied by number of squares gives strap resistance; parallel straps reduce effective resistance; via resistance (1-5Ω per via at 7nm) becomes significant, requiring via arrays for low-resistance connections
• Iterative Optimization: initial grid sized based on power estimates → IR drop analysis identifies hotspots → add straps or widen existing straps in violation regions → re-analyze; Innovus and ICC2 automate this loop with built-in IR drop repair
• Trade-offs: wider/denser power mesh reduces IR drop but consumes routing resources and increases capacitance (dynamic power); typical power grid uses 10-20% of available metal resources; balance between IR drop targets and routing congestion

Decoupling Capacitor Strategy:

• On-Chip Decap: MOS capacitors or MIM (metal-insulator-metal) capacitors placed in white space to provide local charge reservoir; responds to high-frequency current transients faster than package-level capacitors; typical decap density 5-15% of core area
• Placement Strategy: decap cells placed near high-activity blocks (clock buffers, arithmetic units) and in routing white space; automated decap insertion tools (Cadence and Synopsys) place decap to minimize dynamic IR drop hotspots
• Frequency Response: on-chip decap effective for >100MHz transients; package decap handles 1-100MHz; board-level decap handles <1MHz; complete PDN requires coordinated design across all three levels
• Decap Cell Libraries: standard cell libraries include multiple decap cell sizes (1×, 2×, 4×, 8× unit capacitance); filler cells often include small decap to utilize all available space; advanced nodes use deep trench capacitors for higher density

Advanced Techniques:

• Power Gating: isolates power supply to idle blocks using header/footer switches; reduces leakage power by 10-100× but requires careful PDN design to handle switch resistance and inrush current during wake-up
• Voltage Islands: different blocks operate at different supply voltages (e.g., 1.0V for logic, 0.7V for memory); requires separate power grids with level shifters at domain boundaries; complicates PDN design but enables significant power savings
• Backside Power Delivery: emerging technique at 3nm and beyond places power grid on backside of wafer using through-silicon vias (TSVs) or backside metallization; frees front-side metal layers entirely for signal routing, improving density and performance
• Machine Learning Optimization: recent research applies ML to predict IR drop hotspots early in design and optimize grid topology; reduces analysis iterations and improves PPA by 3-5% compared to traditional heuristics

Power grid design is the foundation of reliable chip operation — an inadequate PDN causes timing failures, functional errors, and reliability issues that cannot be fixed after tapeout, making robust power delivery one of the most critical and non-negotiable aspects of physical design at advanced nodes.