The power delivery network (PDN) is the entire electrical path that carries current from the voltage regulator to every transistor on the die — the board planes, the package, the solder bumps, and the on-chip metal power grid — together with the decoupling capacitors that hold the voltage steady along the way. Its job sounds trivial: deliver a clean, constant voltage. In practice it is one of the hardest problems in modern chip design, because billions of transistors switch in lockstep and pull huge, spiky currents through thin, imperfect metal. Any moment the voltage sags below spec, timing paths fail and the chip crashes. As high-performance parts now draw hundreds of amps at well under a volt, the PDN — not the transistor — has become a first-order limiter, and that pressure is what pushed the industry to backside power delivery.\n\nA PDN must hold voltage steady while delivering enormous, rapidly changing current through imperfect metal. The regulator sets a nominal rail — say 0.75 V — but everything between it and the transistors has resistance and inductance. A modern GPU or CPU can draw several hundred amps, so the network's target impedance has to stay in the single-digit milliohms across a very wide frequency band. Miss that target and the rail moves. Two distinct failure modes dominate, one static and one dynamic: IR drop and di/dt droop.\n\nIR drop is the static voltage loss from resistance: current times grid resistance. The on-chip power grid is a mesh of metal wires, and every wire has finite resistance, so current flowing through it drops voltage by V = I·R — transistors far from a supply connection see less than the nominal rail. The same current density also drives electromigration, slowly eroding the metal. Designers fight IR drop with wider and thicker upper-level metal, denser grids, and more supply taps, but there is no free lunch: every track spent on power is a track not available for signal routing, so the grid steals area and wiring resources from the logic it feeds.\n\ndi/dt droop is the dynamic problem: inductance resists sudden current changes, so voltage sags on load steps. When a large block wakes up, its current demand can jump in a nanosecond, and the inductance of the package and board path opposes that change with a voltage of L·di/dt — the rail droops before the regulator can react. The worst case is the resonance between package inductance and on-die capacitance, the notorious "first droop." Because the design must survive this worst-case sag, droop sets the voltage guardband: engineers either raise the operating voltage or lower the clock to stay safe, and both cost power and performance directly.\n\nDecoupling capacitors are the fix, arranged in a hierarchy that supplies charge at every timescale. The regulator is far away and slow, so local reservoirs of charge are stationed at each level of the network and each covers a different frequency band: bulk capacitors on the board absorb slow microsecond transients, package capacitors handle the mid-frequency range, and on-die capacitance — MIM caps, MOS decap, and the intrinsic gate and well capacitance — answers the fastest sub-nanosecond spikes right where they happen. Stacked together, these tiers flatten the PDN's impedance-versus-frequency curve below the target line. The catch is that on-die decoupling consumes silicon area that competes directly with logic.\n\nBackside power delivery is the structural answer: move the whole PDN to the back of the wafer. Traditionally power and signal share the same front-side metal stack, forcing them to compete for the same tracks and leaving the power wires thin and resistive. Backside power delivery — Intel's PowerVia and the broader BSPDN trend — builds the power grid on the back of the silicon with buried rails and nano-scale through-silicon vias, freeing the front side entirely for signals and giving power much thicker, lower-resistance metal. That cuts IR drop and di/dt droop at the same time, which is exactly why it is arriving at the 2 nm-class nodes: the network, not the device, had become the bottleneck.\n\n| Problem / element | Physical cause | Symptom | Mitigation |\n|---|---|---|---|\n| IR drop (static) | Grid resistance × current (V = I·R) | Cells far from a tap undervolt; electromigration | Thicker/wider metal, denser grid, more supply taps |\n| di/dt droop (dynamic) | Package/board inductance on load steps (L·di/dt) | Transient rail sag, timing failures | Decap hierarchy, lower inductance, voltage guardband |\n| Decoupling caps | Charge reservoir per frequency band | (the fix — flattens PDN impedance) | Board bulk → package MLCC → on-die MIM/MOS |\n| Backside PDN | Power and signal share front-side metal | Thin, resistive power wires | Move the PDN to the wafer backside (PowerVia) |\n\n``svg\n\n``\n\nThe unhelpful way to think about the PDN is as plumbing — a passive detail the "real" designers can ignore. The useful way is to see it as an active constraint that now shapes the whole chip: a network that must hold a sub-volt rail rock-steady while hundreds of amps slam on and off in nanoseconds, fighting resistance (IR drop) and inductance (di/dt droop) with a carefully tuned hierarchy of decoupling capacitors that each cover a slice of the frequency spectrum. When even that stops being enough, you change the structure itself and move the entire power network to the back of the wafer so it no longer competes with signals for metal. Read power delivery through a hold-the-rail-steady-at-every-timescale lens rather than a just-connect-it-to-VDD lens, and the power grid, the decap tiers, the voltage guardband, and backside power delivery stop looking like separate concerns and resolve into one: getting clean current to the transistor is now as hard as building the transistor.