Unified Power Format (UPF) and Power-Intent Design is the IEEE 1801 standard methodology for specifying and implementing multi-voltage, power-gating, and retention strategies in SoC designs — where the UPF file declaratively defines power domains, supply nets, isolation cells, level shifters, and retention registers, enabling EDA tools to automatically insert the required power management hardware and verify that the design operates correctly across all power states.

Why UPF Is Essential

Modern SoCs have 10-50+ power domains, each independently controllable: CPU cores power-gate during idle (voltage=0), GPU operates at variable voltage (DVFS), always-on domains maintain state during sleep, and I/O domains use different voltage levels. Without a formal specification, the interactions between these domains (>100 power state transitions) are impossible to manually track and verify.

UPF Power Concepts

• Power Domain: A group of logic cells sharing the same primary power supply. Each domain can be independently powered on/off and voltage-scaled.
• Supply Net: The electrical power rail (VDD, VSS) feeding a domain. UPF maps supply nets to specific voltage values in each power state.
• Power State Table (PST): Defines all legal combinations of supply states across all domains. A 20-domain SoC might have 50-100 legal power states.

Power Management Cells

• Isolation Cell: Clamps the output of a powered-off domain to a safe value (0 or 1) to prevent floating signals from corrupting powered-on domains. Placed at every signal crossing from a switchable domain to an always-on or independently powered domain.
• Level Shifter: Converts signal voltage levels between domains operating at different voltages (e.g., 0.8V core to 1.8V I/O). Required at every signal crossing between voltage-incompatible domains.
• Retention Register: A flip-flop with a secondary (always-on) power supply that saves its state when the primary supply is removed. Enables fast wake-up (restore state from retention instead of re-initializing) with minimal always-on area overhead.
• Power Switch (Header/Footer): Large PMOS (header) or NMOS (footer) transistors that gate the power supply to a domain. Controlled by a power management controller. Hundreds of switches distributed across the domain provide low on-resistance and controlled inrush current during power-up.

UPF Verification Flow

1. UPF-Aware Simulation: The simulator models supply states, turning off logic in powered-down domains and corrupting outputs. Verifies that the design functions correctly across power state transitions. 2. Formal Power Verification: Tools (Synopsys VC LP, Cadence Conformal Low Power) formally verify that isolation, level shifting, and retention are correctly applied at all domain boundaries — no missing cells, no wrong polarity. 3. Implementation: Synthesis and P&R tools read the UPF and automatically insert isolation cells, level shifters, retention registers, and power switches at the specified locations.

UPF is the contract between the power architect and the implementation tools — encoding the complete power management intent in a machine-readable format that ensures the design functions correctly in every power state, from full performance to deep sleep and every transition between them.