Backside Power Delivery Network (BSPDN) — routing power supply wires through the back of the silicon wafer instead of through the front-side metal stack, freeing signal routing resources.
Problem
- Traditional chips route both signals AND power through the same front-side metal layers
- Power wires are thick and consume valuable routing resources
- IR drop (voltage drop) across long front-side power routes limits performance
Solution
- Thin the wafer to ~5um from the backside
- Create nano-TSVs (through-silicon vias) from the back to reach transistor power rails
- Build dedicated power delivery network on the backside
- Signal routing uses only front-side metals — more space, shorter wires
Benefits
- 30-50% reduction in IR drop
- Free up 2-3 front-side metal layers for signal routing
- Lower power delivery resistance
- Enables higher transistor density and performance
Implementations
- Intel PowerVia (Intel 20A/14A): First production backside power. Demonstrated working test chips
- imec: Leading research consortium for BSPDN
- TSMC and Samsung developing their own approaches
BSPDN is considered the next major process innovation after GAA transistors — expected to be standard at 2nm and below.