Process Design Rules and Design Rule Manual (DRM) codify manufacturing constraints derived from process capability, enabling correct-by-design VLSI layouts while accounting for lithography/etch proximity effects and electrical performance margins.
Design Rule Hierarchy:
- Lithographic capability: minimum feature size (e.g., 20 nm gate pitch)
- Etch capability: define etch-margin rules (avoid pinch-off, bridging)
- Implant/dopant: diffusion rules (lateral spread, isolation)
- Metrology: CD uniformity, overlay (alignment) tolerance
- Parametric testing: device behavior (Vt, matching, leakage)
- Reliability: hot-carrier, ESD, electromigration
Minimum Design Rules:
- Width rule: minimum feature dimension (gate length, metal width)
- Spacing rule: minimum distance between features
- Area rule: minimum region area (SRAM capacitor requirements)
- Enclosure rule: geometry wrapping another layer (e.g., contact enclosure in pad)
Proximity Effects and Interaction Rules:
- Pattern density effect: isolated feature vs. dense cluster etch differently
- Forbidden pitch: specific spacing/period difficult to pattern (resist resonance)
- Recommended pitch: design toward achievable repeating pattern
- Litho-etch interaction: combine lithographic + etch rules
- CMP interaction: pattern density affects polish rate (dishing risk in dense regions)
Antenna Rules:
- Antenna effect: accumulated charge on floating conducting structure
- Risk: gate oxide damage during plasma processing (implant/etch)
- Antenna ratio: ratio of gate area to source/drain area
- Rule limit: antenna ratio <100:1 typical (must route during routing)
- ESD protection: antenna-sensitive gates require input buffer
- Checking: automatic DRC antenna rule enforcement
Density Rules:
- CMP density: metal layer must maintain minimum density (prevents dishing)
- Dummy fill: add non-functional geometry to achieve density requirement
- Density window: band of densities to avoid (resonance modes)
- Local vs. global density: checked at different scales
Electrical Performance Rules:
- Voltage domain crossing: level shifter required between different voltage domains
- Clock domain crossing: synchronizer required between asynchronous clocks
- Routing density: avoid congestion (improves timing, reduces resistance)
- IR drop: power grid geometry ensures voltage drop <5% typical
DRM Development Flow:
- Characterization: build test vehicles, measure electrical parameters
- Variation study: temperature, voltage, process corner sweep
- Yield modeling: relate design rules to expected yield
- Design windows: define safe operating region (yield >80% target)
- Rule hardening: conservative margin (design rule >> process capability)
Design-Technology Co-Optimization (DTCO):
- Traditional: process developed independently, designers adapt
- DTCO approach: co-design process + design rules for optimal PPA
- Rule relaxation: relax expensive rules in non-critical areas (cost reduction)
- Iteration: design rules refined as yield learning accumulates
DRM Documentation:
- Layered definitions: each layer defines its own rules
- Layer stack diagram: show all layers and their relative height
- Spacing/width tables: rules for each layer pair interaction
- Resistance/capacitance: parasitics for interconnect (Ω/square, pF/length)
- Physical verification deck: rule file for DRC tools (Calibre, Hercules)
Tool Interaction:
- Design entry: designer draws layout (adhering to DRC rules)
- DRC checker: automated tool verifies all rules (Calibre, Cleaner)
- LVS (layout-vs-schematic): verify connectivity matches schematic
- Physical verification: timing, extraction, parasitic validation
Rule Scaling and Technology Migration:
- Node-to-node variation: rules change significantly between nodes
- Technology file: foundry provides rule updates for migration
- Legacy designs: legacy rules often incompatible with new technology
- Re-qualification: old designs require re-taping or major redesign
Economic Impact:
- Design cycle: DRM clarity reduces designer learning curve
- Yield improvement: conservative rules improve first-pass yield
- Cost per rule: aggressive rules reduce area (lower cost/die)
- Trade-off: rule aggressiveness vs. yield risk (foundry vs. customer risk tolerance)
Design rules represent social contract between foundry/designers—balancing process capability disclosure (foundry competitive concern) with designer need for clear, conservative constraints enabling predictable yield and electrical performance.