Semiconductor Process Nodes are the generational labels used to describe successive advances in chip manufacturing technology, originally representing a physical feature size (gate length or metal pitch) but now serving as marketing terminology that captures a bundle of improvements in transistor density, power efficiency, and performance — making the "nm" number a trademarked capability designation rather than a literal physical measurement.

Why "nm" No Longer Means Nanometers

<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
  <rect x="0" y="0" width="760" height="470" fill="#0d1117"/>
  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Process Node Roadmap — Transistor Scaling</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">nm label ≠ physical gate length — it is a density/performance marketing generation</text>

  <!-- Transistor cross-section evolution -->
  <rect x="30" y="65" width="700" height="160" rx="6" fill="#080d14" stroke="#233043" stroke-width="1"/>
  <text x="380" y="84" fill="#e6edf3" font-size="11" font-weight="600" text-anchor="middle">Transistor Architecture Evolution</text>

  <!-- Planar (28nm+) -->
  <rect x="55" y="100" width="130" height="105" rx="4" fill="#0d1117" stroke="#334155" stroke-width="0.6"/>
  <text x="120" y="115" fill="#60a5fa" font-size="9" font-weight="600" text-anchor="middle">Planar (28nm+)</text>
  <!-- Gate on top of flat channel -->
  <rect x="75" y="160" width="90" height="12" rx="1" fill="#1e3a5f"/>
  <text x="120" y="169" fill="#93c5fd" font-size="6.5" text-anchor="middle">substrate</text>
  <rect x="95" y="145" width="50" height="14" rx="1" fill="#2d6b55" stroke="#34d399" stroke-width="0.8"/>
  <text x="120" y="155" fill="#6ee7b7" font-size="7" text-anchor="middle">gate</text>
  <rect x="75" y="150" width="16" height="10" rx="1" fill="#f59e0b" opacity="0.6"/>
  <text x="83" y="148" fill="#fbbf24" font-size="5.5" text-anchor="middle">S</text>
  <rect x="149" y="150" width="16" height="10" rx="1" fill="#f59e0b" opacity="0.6"/>
  <text x="157" y="148" fill="#fbbf24" font-size="5.5" text-anchor="middle">D</text>
  <text x="120" y="195" fill="#6b7684" font-size="7.5" text-anchor="middle">gate controls top only</text>

  <!-- Arrow -->
  <path d="M188,155 L208,155" fill="none" stroke="#3a4453" stroke-width="1"/>
  <polygon points="206,152 212,155 206,158" fill="#3a4453"/>

  <!-- FinFET (16nm–5nm) -->
  <rect x="215" y="100" width="145" height="105" rx="4" fill="#0d1117" stroke="#334155" stroke-width="0.6"/>
  <text x="287" y="115" fill="#34d399" font-size="9" font-weight="600" text-anchor="middle">FinFET (16–5nm)</text>
  <!-- 3D fin -->
  <rect x="265" y="160" width="80" height="12" rx="1" fill="#1e3a5f"/>
  <rect x="285" y="132" width="12" height="30" rx="1" fill="#34d399" opacity="0.7"/>
  <rect x="302" y="132" width="12" height="30" rx="1" fill="#34d399" opacity="0.7"/>
  <rect x="319" y="132" width="12" height="30" rx="1" fill="#34d399" opacity="0.7"/>
  <rect x="278" y="138" width="60" height="18" rx="2" fill="none" stroke="#fbbf24" stroke-width="1" stroke-dasharray="3,2"/>
  <text x="308" y="150" fill="#fbbf24" font-size="6.5" text-anchor="middle">gate wraps 3 sides</text>
  <text x="287" y="195" fill="#6b7684" font-size="7.5" text-anchor="middle">3D fin → better control</text>

  <!-- Arrow -->
  <path d="M363,155 L383,155" fill="none" stroke="#3a4453" stroke-width="1"/>
  <polygon points="381,152 387,155 381,158" fill="#3a4453"/>


  <!-- GAA / Nanosheet (3nm–) -->
  <rect x="390" y="100" width="150" height="105" rx="4" fill="#0d1117" stroke="#334155" stroke-width="0.6"/>
  <text x="465" y="115" fill="#a78bfa" font-size="9" font-weight="600" text-anchor="middle">GAA Nanosheet (3nm–)</text>
  <!-- Stacked nanosheets -->
  <rect x="425" y="160" width="80" height="12" rx="1" fill="#1e3a5f"/>
  <rect x="438" y="132" width="50" height="6" rx="1" fill="#a78bfa" opacity="0.6"/>
  <rect x="438" y="141" width="50" height="6" rx="1" fill="#a78bfa" opacity="0.6"/>
  <rect x="438" y="150" width="50" height="6" rx="1" fill="#a78bfa" opacity="0.6"/>
  <rect x="432" y="130" width="62" height="30" rx="2" fill="none" stroke="#fbbf24" stroke-width="1" stroke-dasharray="3,2"/>
  <text x="463" y="127" fill="#fbbf24" font-size="6.5" text-anchor="middle">gate wraps all 4 sides</text>
  <text x="465" y="195" fill="#6b7684" font-size="7.5" text-anchor="middle">stacked sheets = more Idrive</text>

  <!-- Arrow -->
  <path d="M543,155 L563,155" fill="none" stroke="#3a4453" stroke-width="1"/>
  <polygon points="561,152 567,155 561,158" fill="#3a4453"/>

  <!-- CFET (future) -->
  <rect x="570" y="100" width="140" height="105" rx="4" fill="#0d1117" stroke="#334155" stroke-width="0.6"/>
  <text x="640" y="115" fill="#f87171" font-size="9" font-weight="600" text-anchor="middle">CFET (A14 / 1nm)</text>
  <!-- Stacked NMOS/PMOS -->
  <rect x="600" y="160" width="80" height="12" rx="1" fill="#1e3a5f"/>
  <rect x="615" y="130" width="50" height="14" rx="2" fill="#1c1633" stroke="#a78bfa" stroke-width="0.6"/>
  <text x="640" y="140" fill="#c4b5fd" font-size="6.5" text-anchor="middle">PMOS</text>
  <rect x="615" y="148" width="50" height="14" rx="2" fill="#14261f" stroke="#34d399" stroke-width="0.6"/>
  <text x="640" y="158" fill="#6ee7b7" font-size="6.5" text-anchor="middle">NMOS</text>
  <text x="640" y="195" fill="#6b7684" font-size="7.5" text-anchor="middle">N+P stacked → 2× density</text>

  <!-- Density chart -->
  <rect x="30" y="238" width="450" height="180" rx="6" fill="#080d14" stroke="#233043" stroke-width="1"/>
  <text x="255" y="258" fill="#e6edf3" font-size="11" font-weight="600" text-anchor="middle">Transistor Density (MTr/mm²) by Node</text>

  <!-- Y-axis -->
  <line x1="75" y1="270" x2="75" y2="400" stroke="#3a4453" stroke-width="0.8"/>
  <text x="68" y="282" fill="#6b7684" font-size="7" text-anchor="end">300</text>
  <text x="68" y="310" fill="#6b7684" font-size="7" text-anchor="end">200</text>
  <text x="68" y="340" fill="#6b7684" font-size="7" text-anchor="end">100</text>
  <text x="68" y="370" fill="#6b7684" font-size="7" text-anchor="end">50</text>
  <text x="68" y="398" fill="#6b7684" font-size="7" text-anchor="end">10</text>

  <!-- X-axis -->
  <line x1="75" y1="400" x2="460" y2="400" stroke="#3a4453" stroke-width="0.8"/>

  <!-- Bars -->
  <rect x="95" y="385" width="35" height="15" rx="2" fill="#60a5fa"/>
  <text x="112" y="412" fill="#6b7684" font-size="7" text-anchor="middle">28nm</text>
  <text x="112" y="382" fill="#93c5fd" font-size="7" text-anchor="middle">10</text>

  <rect x="145" y="370" width="35" height="30" rx="2" fill="#60a5fa"/>
  <text x="162" y="412" fill="#6b7684" font-size="7" text-anchor="middle">14nm</text>
  <text x="162" y="367" fill="#93c5fd" font-size="7" text-anchor="middle">30</text>

  <rect x="195" y="355" width="35" height="45" rx="2" fill="#34d399"/>
  <text x="212" y="412" fill="#6b7684" font-size="7" text-anchor="middle">7nm</text>
  <text x="212" y="352" fill="#6ee7b7" font-size="7" text-anchor="middle">65</text>

  <rect x="245" y="335" width="35" height="65" rx="2" fill="#34d399"/>
  <text x="262" y="412" fill="#6b7684" font-size="7" text-anchor="middle">5nm</text>
  <text x="262" y="332" fill="#6ee7b7" font-size="7" text-anchor="middle">130</text>

  <rect x="295" y="310" width="35" height="90" rx="2" fill="#a78bfa"/>
  <text x="312" y="412" fill="#6b7684" font-size="7" text-anchor="middle">3nm</text>
  <text x="312" y="307" fill="#c4b5fd" font-size="7" text-anchor="middle">200</text>

  <rect x="345" y="285" width="35" height="115" rx="2" fill="#f87171"/>
  <text x="362" y="412" fill="#6b7684" font-size="7" text-anchor="middle">2nm</text>
  <text x="362" y="282" fill="#fca5a5" font-size="7" text-anchor="middle">300+</text>

  <rect x="395" y="272" width="35" height="128" rx="2" fill="#f87171" opacity="0.5" stroke-dasharray="3,2" stroke="#f87171" stroke-width="0.8"/>
  <text x="412" y="412" fill="#6b7684" font-size="7" text-anchor="middle">A14</text>
  <text x="412" y="269" fill="#fca5a5" font-size="7" text-anchor="middle">400+?</text>


  <!-- Right panel: what "nm" actually means -->
  <rect x="500" y="238" width="230" height="180" rx="6" fill="#080d14" stroke="#233043" stroke-width="1"/>
  <text x="615" y="258" fill="#e6edf3" font-size="10" font-weight="600" text-anchor="middle">What "nm" Actually Means</text>

  <text x="515" y="280" fill="#f87171" font-size="9" font-weight="600">≠ gate length</text>
  <text x="515" y="296" fill="#8b98a5" font-size="8">The nm label has been a</text>
  <text x="515" y="310" fill="#8b98a5" font-size="8">marketing name since ~22nm.</text>

  <text x="515" y="332" fill="#34d399" font-size="9" font-weight="600">= density generation</text>
  <text x="515" y="348" fill="#8b98a5" font-size="8">TSMC N3: gate pitch 48nm</text>
  <text x="515" y="362" fill="#8b98a5" font-size="8">metal pitch 21nm (actual dims)</text>

  <text x="515" y="384" fill="#f59e0b" font-size="9" font-weight="600">Naming varies by fab:</text>
  <text x="515" y="400" fill="#6b7684" font-size="8">TSMC N3 ≈ Samsung 3GAE</text>
  <text x="515" y="414" fill="#6b7684" font-size="8">Intel 4 ≈ TSMC N3 (density)</text>

  <!-- Footer -->
  <text x="380" y="440" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Each full-node shrink: ~2× density, 25–30% speed gain, or 40–50% power reduction</text>
  <text x="380" y="458" fill="#6b7684" font-size="11" text-anchor="middle">The "nm" number is a brand — actual gate pitch, fin pitch, and metal pitch define the real shrink.</text>
</svg>

In the 1990s and early 2000s, the process node name corresponded directly to the transistor gate length:

• 250nm (1997): Gate length = 250nm
• 130nm (2001): Gate length = 130nm
• 90nm (2004): Gate length = 90nm

This correspondence ended around 2003-2007. Today:

• TSMC N3 (3nm): Minimum metal pitch ~20nm; smallest feature ~12nm — nothing is actually 3nm
• Intel 7 (previously called 10nm): Renamed to match competitor marketing language
• TSMC N2 (2nm): Gate-all-around nanosheets, smallest features ~10nm

The node name is now a relative performance/density label. TSMC N3 is denser and more power-efficient than N5 — but the "3" is a generational marker, not a dimension.

Node Roadmap and Transistor Architecture Evolution

Key Nodes and Their Significance

28nm — The Last Planar Node

• Cost: ~$3,000/wafer (very mature)
• Used for: MCUs, IoT chips, display drivers, analog, automotive
• Why it persists: Cost-optimized, abundant foundry capacity, no EUV needed
• Still in production at TSMC, Samsung, GlobalFoundries, UMC, SMIC

7nm — First Mass EUV Production

• TSMC 7nm (2018): First node to use EUV lithography in production at scale
• AMD Zen 2 (2019), Apple A13 Bionic — transformed PC and mobile performance
• 160M transistors/mm² for TSMC N7
• Wafer cost: ~$9,000

5nm — Mobile AI Mainstream

• TSMC N5 (2020), Samsung 5LPE
• Apple M1 (2020): First laptop processor to demolish x86 performance-per-watt
• 171M transistors/mm² for TSMC N5
• Wafer cost: ~$13,000

3nm — FinFET Limit

• TSMC N3 (2022), N3E (2023): Still FinFET architecture
• Samsung 3GAE: First commercial GAA node (2022), lower yield than TSMC initially
• 291M transistors/mm² for TSMC N3E
• Apple A17 Pro, M3 series manufactured on TSMC N3
• Wafer cost: ~$18,000-$20,000

2nm — GAA Transition

• TSMC N2 (2025): Industry's debut of Gate-All-Around (GAA) in volume production
• Samsung SF2 (2025): Samsung's 2nm GAA
• Intel 20A/18A (2025): Intel's GAA (RibbonFET) with PowerVia backside power delivery
• ~400M+ transistors/mm² target
• Wafer cost: $20,000-$25,000+

Why Process Nodes Matter for AI Chips

AI chips are the most voracious consumers of leading-edge process nodes:

Each new node delivers approximately:

• 15-20% performance improvement at same power
• 30-40% power reduction at same performance
• ~1.6x density increase (more transistors per mm²)

Economics: The Leading-Edge Cost Spiral

This cost explosion is driving the chiplet revolution: only the most performance-sensitive circuits (CPU cores, GPU cores) use leading-edge nodes, while I/O, analog, and memory use older, cheaper nodes. NVIDIA's GB200 uses TSMC N3 for the compute die and N5 for the NVLink die.

CHIPS Act and Geopolitics

Semiconductor manufacturing geography has become a national security issue:

• TSMC: 60% of global advanced logic capacity (Taiwan) — building factories in Arizona (N4), Japan (N12/N6), Germany (N22/N28)
• Samsung: Second largest advanced foundry (South Korea) — Taylor, Texas fab under construction
• Intel Foundry: Intel 18A targets European and US market; $8.5B CHIPS Act funding
• SMIC (China): Limited to ~7nm (N+1/N+2) due to US export controls on EUV scanners
• Export Controls: BIS (Bureau of Industry and Security) restricts EUV export to China, blocking <7nm access

Process node leadership determines AI chip leadership — and AI chip leadership increasingly determines economic and military competitiveness.