QFN (Quad Flat No-Lead) is a surface-mount IC package where all electrical leads are on the bottom perimeter — flush with or recessed into the package body — with no protruding gull-wing or J-leads. The die is mounted to an exposed copper die-attach pad (DAP) that doubles as the primary thermal path to the PCB.

Key construction elements: silicon die wire-bonded to a copper lead frame, encapsulated in epoxy mold compound, with the bottom DAP and perimeter leads solderable directly to PCB land patterns.

Thermal performance is the QFN's main advantage over leaded packages: the exposed DAP conducts ~50–80% of heat, achieving junction-to-board resistance of 7–12 C/W versus 35+ C/W through wire-bond leads alone. PCB thermal vias under the DAP further reduce impedance.

Signal integrity: bond wires (25 µm Au or 20 µm Cu) add inductance (~1 nH/mm) and limit RF bandwidth — typically usable to ~6 GHz. For >10 GHz or high-power applications, flip-chip or HVQFN variants with integrated ground planes are preferred.

Manufacturing: QFN packages are produced on copper lead frames, molded in strip format, and singulated by saw dicing. They are assembled via SMT reflow at 260°C peak (SAC305 solder), with stencil printing controlling thermal pad voiding to <25% for reliable Rth.

AI/ML context: QFN is standard for edge AI support ICs — PMICs, clock buffers, SerDes retimers, and small inference accelerators (<5W). Large AI training/inference chips (>50W) require flip-chip BGA due to thermal and I/O density requirements that QFN cannot meet.

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<!-- PANEL 1: QFN Cross-Section (x=8,y=8,w=234,h=290) -->
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<text x="125" y="27" text-anchor="middle" class="hdr">QFN Cross-Section</text>

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<text x="125" y="76" text-anchor="middle" class="sm dim">(active circuitry)</text>

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<!-- Left bond wires -->
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<text x="206" y="134" class="sm dim">Leads</text>

<!-- Mold compound body -->
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<text x="125" y="172" text-anchor="middle" class="sm" fill="#3fb950" opacity="0.8">Epoxy Mold Compound</text>

<!-- Exposed pad (thermal) at bottom center -->
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<text x="125" y="220" text-anchor="middle" class="sm" fill="#388bfd" font-weight="700">Exposed Thermal Pad (DAP)</text>

<!-- PCB -->
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<!-- Thermal pad solder -->
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<!-- Thermal arrow down -->
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<text x="125" y="300" text-anchor="middle" class="sm dim">Typical: 3x3mm to 12x12mm body</text>

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<!-- Die pad -->
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<!-- Bond wire -->
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<!-- Lead -->
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<!-- Thermal path comparison -->
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<!-- Bars for Rth comparison -->
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<text x="408" y="229" class="sm" fill="#ff7b72">Wire-bond path ~35 C/W</text>

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<text x="320" y="245" class="sm" fill="#3fb950">DAP path ~7 C/W</text>

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<text x="348" y="261" class="sm" fill="#388bfd">Flip-chip ~4 C/W</text>

<text x="262" y="278" class="sm dim">DAP = Die-Attach Pad; lower = better</text>
<text x="262" y="292" class="sm dim">QFN DAP: 50-80% heat via exposed pad</text>

<!-- PANEL 3: Package Variants (x=502,y=8,w=250,h=290) -->
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<text x="627" y="27" text-anchor="middle" class="hdr">QFN Variants + Key Parameters</text>

<!-- Variant table -->
<text x="514" y="46" class="sm" fill="#e6edf3" font-weight="700">Package Type</text>
<text x="640" y="46" class="sm" fill="#e6edf3" font-weight="700">Size / Use</text>

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<text x="514" y="64" class="sm">QFN-8</text>
<text x="640" y="64" class="sm dim">2x2mm, LDO/OpAmp</text>

<text x="514" y="78" class="sm">QFN-16</text>
<text x="640" y="78" class="sm dim">3x3mm, MCU/sensor</text>

<text x="514" y="92" class="sm">QFN-32</text>
<text x="640" y="92" class="sm dim">5x5mm, comms IC</text>

<text x="514" y="106" class="sm">QFN-48</text>
<text x="640" y="106" class="sm dim">7x7mm, FPGA/MPU</text>

<text x="514" y="120" class="sm">QFN-64</text>
<text x="640" y="120" class="sm dim">9x9mm, AI accelerator</text>

<text x="514" y="134" class="sm" fill="#d29922">HVQFN</text>
<text x="640" y="134" class="sm dim">Heatsink variant, RF PA</text>

<text x="514" y="148" class="sm" fill="#3fb950">WQFN</text>
<text x="640" y="148" class="sm dim">Thin profile, wearables</text>

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<!-- Key spec callouts -->
<text x="514" y="170" class="sm" fill="#e6edf3" font-weight="700">Key Spec Parameters:</text>

<text x="514" y="184" class="sm dim">Lead pitch:</text>
<text x="590" y="184" class="sm" fill="#388bfd">0.4 / 0.5 / 0.65 mm</text>

<text x="514" y="198" class="sm dim">Body height:</text>
<text x="590" y="198" class="sm" fill="#388bfd">0.75 – 1.0 mm</text>

<text x="514" y="212" class="sm dim">Lead material:</text>
<text x="590" y="212" class="sm" fill="#388bfd">Cu alloy (C194/C7025)</text>

<text x="514" y="226" class="sm dim">Plating:</text>
<text x="590" y="226" class="sm" fill="#388bfd">NiPdAu / matte Sn</text>

<text x="514" y="240" class="sm dim">Bond wire:</text>
<text x="590" y="240" class="sm" fill="#388bfd">Au 25um or Cu 20um</text>

<text x="514" y="254" class="sm dim">MSL rating:</text>
<text x="590" y="254" class="sm" fill="#388bfd">MSL 1–3 (JEDEC J-STD-020)</text>

<text x="514" y="268" class="sm dim">Theta-JA (typ):</text>
<text x="590" y="268" class="sm" fill="#ff7b72">25–50 C/W (air)</text>

<text x="514" y="282" class="sm dim">Theta-JB (DAP):</text>
<text x="590" y="282" class="sm" fill="#3fb950">7–12 C/W (mounted)</text>

<!-- CARD 1: Assembly + Reliability -->
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<text x="125" y="322" text-anchor="middle" class="hdr">Assembly + Reliability</text>
<text x="18" y="338" class="sm" fill="#e6edf3" font-weight="700">SMT Assembly:</text>
<text x="18" y="352" class="sm dim">Stencil aperture = 1:1 or 1.1:1 for</text>
<text x="18" y="364" class="sm dim">thermal pad (reduce voiding &lt;25%)</text>
<text x="18" y="376" class="sm dim">Reflow: peak 260C, SAC305 solder</text>
<text x="18" y="388" class="sm" fill="#e6edf3" font-weight="700">Reliability Tests:</text>
<text x="18" y="400" class="sm dim">TC: -40/+125C, 1000 cycles (AEC-Q100)</text>
<text x="18" y="412" class="sm dim">HAST: 130C/85%RH/96h (moisture)</text>
<text x="18" y="424" class="sm dim">Drop: JESD22-B111 (mobile apps)</text>
<text x="18" y="436" class="sm dim">Warpage: &lt;100um (IPC-7095D)</text>
<text x="18" y="448" class="sm dim">X-ray / SAM: void inspection post-reflow</text>
<text x="18" y="460" class="sm dim">Linescan: wire pull &gt;5g, ball shear &gt;30g</text>

<!-- CARD 2: QFN vs BGA vs Flip-Chip -->
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<text x="372" y="322" text-anchor="middle" class="hdr">QFN vs BGA vs Flip-Chip</text>
<text x="260" y="338" class="sm" fill="#3fb950" font-weight="700">QFN advantages:</text>
<text x="260" y="350" class="sm dim">Low cost, compact, good thermal (DAP)</text>
<text x="260" y="362" class="sm dim">No solder balls — robust to vibration</text>
<text x="260" y="374" class="sm dim">Direct PCB inspection difficult (no x-ray pads)</text>
<text x="260" y="386" class="sm" fill="#388bfd" font-weight="700">BGA advantages:</text>
<text x="260" y="398" class="sm dim">Higher I/O density, better signal integrity</text>
<text x="260" y="410" class="sm dim">X-ray inspectable; suits high-pin-count SoCs</text>
<text x="260" y="422" class="sm" fill="#d29922" font-weight="700">Flip-Chip advantages:</text>
<text x="260" y="434" class="sm dim">Shortest electrical path (direct bump to die)</text>
<text x="260" y="446" class="sm dim">Lowest Rth-JB; required for &gt;50W AI chips</text>
<text x="260" y="458" class="sm dim">QFN: best for &lt;5W edge AI inference ICs</text>

<!-- CARD 3: AI Chip Context -->
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<text x="627" y="322" text-anchor="middle" class="hdr">QFN in AI Edge Systems</text>
<text x="514" y="338" class="sm" fill="#3fb950" font-weight="700">Typical AI edge use cases:</text>
<text x="514" y="352" class="sm dim">NPU companion (clock/power mgmt) QFN-32</text>
<text x="514" y="364" class="sm dim">Always-on keyword detector QFN-16</text>
<text x="514" y="376" class="sm dim">PMIC for inference ASIC QFN-48/64</text>
<text x="514" y="388" class="sm" fill="#388bfd" font-weight="700">Thermal management:</text>
<text x="514" y="400" class="sm dim">AI inference: 0.5–3W — QFN DAP sufficient</text>
<text x="514" y="412" class="sm dim">Training ASICs: &gt;100W — flip-chip BGA only</text>
<text x="514" y="424" class="sm dim">Thermal vias under DAP critical for junction temp</text>
<text x="514" y="436" class="sm" fill="#d29922" font-weight="700">Industry examples:</text>
<text x="514" y="448" class="sm dim">Ambiq Apollo MCU QFN-48: ultra-low-power AI</text>
<text x="514" y="460" class="sm dim">Syntiant NDP120: always-on NLP in QFN-48</text>
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